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x 36-bit. HM62G36256 Datasheet |
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HM62G36256 Series
8M Synchronous Fast Static RAM
(256k-word × 36-bit)
ADE-203-1139 (Z)
Preliminary
Rev. 0.0
Jan. 10, 2000
Description
The HM62G36256 is a synchronous fast static RAM organized as 256-kword × 36-bit. It has realized high
speed access time by employing the most advanced CMOS process and high speed circuit designing
technology. It is most appropriate for the application which requires high speed, high density memory and
wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119-
bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
Features
• Power supply: 3.3 V +10%, –5%
• Clock frequency: 200 MHz to 250 MHz
• Internal self-timed late write
• Byte write control (4 byte write selects, one for each 9-bit)
• Optional ×18 configuration
• HSTL compatible I/O
• Programmable impedance output drivers
• User selective input trip-point
• Differential, HSTL clock inputs
• Asynchronous G output control
• Asynchronous sleep mode
• Limited set of boundary scan JTAG IEEE 1149.1 compatible
• Protocol: Single clock register-register mode
Preliminary: The specifications of this device are subject to change without notice. Please contact your
nearest Hitachi’s Sales Dept. regarding specifications.
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HM62G36256 Series
Ordering Information
Type No.
HM62G36256BP-4
HM62G36256BP-5
Access time
2.1 ns
2.5 ns
Cycle time
4.0 ns
5.0 ns
Package
119-bump 1. 27 mm
14 mm × 22 mm BGA (BP-119A)
Pin Arrangement
119-bumps BGA
1234567
A
VDDQ SA0 SA6 NC SA4 SA2 VDDQ
B
NC NC SA7 NC SA8 SA9 NC
C
NC SA14 SA3 VDD SA5 SA1 NC
D
DQc1 DQc0 VSS ZQ VSS DQb0 DQb1
E
DQc2 DQc3 VSS SS VSS DQb3 DQb2
F
VDDQ DQc4 VSS G VSS DQb4 VDDQ
G
DQc6 DQc5 SWEc NC SWEb DQb5 DQb6
H
DQc7 DQc8 VSS NC VSS DQb8 DQb7
J
VDDQ VDD VREF VDD VREF VDD VDDQ
K
DQd7 DQd8 VSS K VSS DQa8 DQa7
L
DQd6 DQd5 SWEd K SWEa DQa5 DQa6
M
VDDQ DQd4 VSS SWE VSS DQa4 VDDQ
N
DQd2 DQd3 VSS SA17 VSS DQa3 DQa2
P
DQd1 DQd0 VSS SA16 VSS DQa0 DQa1
R
NC SA10 M1 VDD M2 SA11 NC
T
NC NC SA12 SA15 SA13 NC ZZ
U
VDDQ TMS TDI TCK TDO NC VDDQ
(Top view)
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Pin Description
Name
VDD
VSS
VDDQ
VREF
K
K
SS
SWE
SAn
SWEx
G
ZZ
ZQ
DQxn
I/O type
Supply
Supply
Supply
Supply
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
M1, M2
TMS
TCK
TDI
TDO
NC
Input
Input
Input
Input
Output
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HM62G36256 Series
Descriptions
Core power supply
Ground
Output power supply
Input reference: provides input reference voltage
Clock input. Active high.
Clock input. Active low.
Synchronous chip select
Synchronous write enable
Synchronous address input
Synchronous byte write enables
Asynchronous output enable
Power down mode select
Output impedance control
Synchronous data input/output
Output protocol mode select
Boundary scan test mode select
Boundary scan test clock
Boundary scan test data input
Boundary scan test data output
No connection
Notes
n = 0, 1, 2...17
x = a, b, c, d
1
x = a, b, c, d
n = 0, 1, 2...8
M1 M2 Protocol
Notes
VSS
VDD
Synchronous register to register operation
2
Notes: 1. ZQ is to be connected to VSS via a resistance RQ where 150 Ω ≤ RQ ≤ 300 Ω, if ZQ = VDDQ or
open, output buffer impedance will be maximum. A case of minimum impedance, it needs to
connect over 120 Ω between ZQ and VSS.
2. There is 1 protocol with mode pin. Mode control pins (M1, M2) are to be tied either VDD or VSS
respectively. The state of the Mode control inputs must be set before power-up and must not
change during device operation. Mode control inputs are not standard inputs and may not meet
VIH or VIL specification. This SRAM is tested only in the synchronous register to register
operation.
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