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Range Version. HM62V16100I Datasheet |
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HM62V16100I Series
Wide Temperature Range Version
16 M SRAM (1-Mword × 16-bit)
REJ03C0060-0200Z
Rev. 2.00
Oct.06.2003
Description
The HM62V16100I Series is 16-Mbit static RAM organized 1-Mword × 16-bit. HM62V16100I Series has
realized higher density, higher performance and low power consumption by employing CMOS process
technology (6-transistor memory cell). It offers low power standby power dissipation; therefore, it is
suitable for battery backup systems. It has the package variations of 48-bump chip size package with 0.75
mm bump pitch and 48-pin plastic TSOPI for high density surface mounting.
Features
• Single 3.0 V supply: 2.7 V to 3.6 V
• Fast access time: 45/55 ns (max)
• Power dissipation:
Active: 9 mW/MHz (typ)
Standby: 1.5 µW (typ)
• Completely static memory.
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output.
Three state output
• Battery backup operation.
2 chip selection for battery backup
• Temperature range: −40 to +85°C
Rev.2.00, Oct.06.2003, page 1 of 23
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HM62V16100I Series
Ordering Information
Type No.
HM62V16100LTI-4
HM62V16100LTI-4SL
HM62V16100LTI-5SL
HM62V16100LBPI-4
HM62V16100LBPI-4SL
HM62V16100LBPI-5SL
Access time
45 ns
45 ns
55 ns
45 ns
45 ns
55 ns
Package
48-pin plastic TSOPI (normal-bend type) (TFP-48DA)
48-bump CSP with 0.75 mm bump pitch (TBP-48F)
Rev.2.00, Oct.06.2003, page 2 of 23
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HM62V16100I Series
Pin Arrangement
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE
CS2
NU
UB
LB
A18
A17
A7
A6
A5
A4
A3
A2
A1
48-pin TSOP
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
A16
BYTE
VSS
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
VSS
CS1
A0
(Top view)
Rev.2.00, Oct.06.2003, page 3 of 23
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