x 8-bit. HM62V8512CI Datasheet

HM62V8512CI 8-bit. Datasheet pdf. Equivalent

HM62V8512CI Datasheet
Recommendation HM62V8512CI Datasheet
Part HM62V8512CI
Description Wide Temperature Range Version4 M SRAM (512-kword x 8-bit)
Feature HM62V8512CI; HM62V8512CI Series Wide Temperature Range Version 4 M SRAM (512-kword × 8-bit) ADE-203-1215A (Z) Re.
Manufacture Hitachi Semiconductor
Datasheet
Download HM62V8512CI Datasheet




Hitachi Semiconductor HM62V8512CI
HM62V8512CI Series
Wide Temperature Range Version
4 M SRAM (512-kword × 8-bit)
ADE-203-1215A (Z)
Rev. 1.0
Feb. 6, 2001
Description
The Hitachi HM62V8512CI is a 4-Mbit static RAM organized 512-kword × 8-bit. HM62V8512CI Series has
realized higher density, higher performance and low power consumption by employing CMOS process
technology (6-transistor memory cell). The HM62V8512CI Series offers low power standby power
dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 32-pin TSOP II.
Features
Single 3.0 V supply: 2.7 V to 3.6 V
Access time: 70 ns (max)
Power dissipation
Active: 6.0 mW/MHz (typ)
Standby: 2.4 µW (typ)
Completely static memory. No clock or timing strobe required
Equal access and cycle times
Common data input and output: Three state output
Directly LV-TTL compatible: All inputs and outputs
Battery backup operation
Operating temperature: –40 to +85˚C
Ordering Information
Type No.
HM62V8512CLTTI-7
Access time
70 ns
Package
400-mil 32-pin plastic TSOP II (TTP-32D)



Hitachi Semiconductor HM62V8512CI
HM62V8512CI Series
Pin Arrangement
A18 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
A0 12
I/O0 13
I/O1 14
I/O2 15
VSS 16
Pin Description
Pin name
A0 to A18
I/O0 to I/O7
CS
OE
WE
VCC
VSS
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
32-pin TSOP
(Top view)
32 VCC
31 A15
30 A17
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
2



Hitachi Semiconductor HM62V8512CI
Block Diagram
LSB
A11
A9
A8
A15
A18
A10
A13
A17
A16
A14
A12
MSB
I/O0
I/O7
CS
WE
OE
HM62V8512CI Series
Row
Decoder
Memory Matrix
2,048 × 2,048
V CC
V SS
Input
Data
Control
••
Column I/O
Column Decoder
LSB A3 A2A1A0 A4 A5A6 A7 MSB
••
Timing Pulse Generator
Read/Write Control
3







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