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x 4-bit. HM62W4100H Datasheet |
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HM62W4100H Series
4M High Speed SRAM (1-Mword × 4-bit)
ADE-203-774D (Z)
Rev. 1.0
Sep. 15, 1998
Description
The HM62W4100H is a 4-Mbit high speed static RAM organized 1-Mword × 4-bit. It has realized high
speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell) and high speed
circuit designing technology. It is most appropriate for the application which requires high speed and high
density memory, such as cache and buffer memory in system. The HM62W4100H is packaged in 400-mil
32-pin SOJ for high density surface mounting.
Features
• Single supply : 3.3 V ± 0.3 V
• Access time 12/15 ns (max)
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Directly TTL compatible
All inputs and outputs
• Operating current : 180/160 mA (max)
• TTL standby current : 60/50 mA (max)
• CMOS standby current : 5 mA (max)
: 1 mA (max) (L-version)
• Data retension current : 0.6 mA (max) (L-version)
• Data retension voltage: 2 V (min) (L-version)
• Center VCC and VSS type pinout
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HM62W4100H Series
Ordering Information
Type No.
HM62W4100HJP-12
HM62W4100HJP-15
HM62W4100HLJP-12
HM62W4100HLJP-15
Access time
12 ns
15 ns
12 ns
15 ns
Package
400-mil 32-pin plastic SOJ (CP-32DB)
Pin Arrangement
HM62W4100HJP/HLJP Series
A0 1
A1 2
A2 3
A3 4
A4 5
CS 6
I/O1 7
VCC
VSS
I/O2
8
9
10
WE 11
A5 12
A6 13
A7 14
A8 15
A9 16
32 A19
31 A18
30 A17
29 A16
28 A15
27 OE
26 I/O4
25 VSS
24 VCC
23 I/O3
22 A14
21 A13
20 A12
19 A11
18 A10
17 NC
(Top view)
2
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Pin Description
Pin name
A0 to A19
I/O1 to I/O4
CS
OE
WE
VCC
VSS
NC
Function
Address input
Data input/output
Chip select
Output enable
Write enable
Power supply
Ground
No connection
HM62W4100H Series
Block Diagram
(LSB)
A1
A17
A7
A11
A16
A2
A6
A5
(MSB)
I/O1
.
.
.
I/O4
WE
CS
Row
decoder
Memory matrix
256 rows × 16 columns ×
256 blocks × 4 bit
(4,194,304 bits)
VCC
VSS
CS
Input
data
control
Column I/O
Column decoder
CS
A10 A8 A9 A19 A12 A13 A14 A0 A18 A15 A3 A4
(LSB)
(MSB)
OE
CS
3
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