4 M SRAM (512-kword x 8-bit)
HM62W8512BI Series
4 M SRAM (512-kword × 8-bit)
ADE-203-1086A (Z) Rev. 1.0 Jul. 13, 1999 Description
The Hitachi HM62W8...
Description
HM62W8512BI Series
4 M SRAM (512-kword × 8-bit)
ADE-203-1086A (Z) Rev. 1.0 Jul. 13, 1999 Description
The Hitachi HM62W8512BI is a 4-Mbit static RAM organized 512-kword × 8-bit. HM62W8512BI Series has realized higher density, higher performance and low power consumption by employing Hi-CMOS process technology. The HM62W8512BI Series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. It is packaged in standard 32-pin TSOP II.
Features
Single 3.3 V supply: 3.3 V ± 0.3V Access time: 70/85 ns (max) Power dissipation Active: 16.5 mW/MHz (typ) Standby: 3.3 µW (typ) Completely static memory. No clock or timing strobe required Equal access and cycle times Common data input and output: Three state output Directly LV-TTL compatible: All inputs and outputs Battery backup operation Operating temperature: –40 to +85˚C
Ordering Information
Type No. HM62W8512BLTTI-7 HM62W8512BLTTI-8 Access time 70 ns 85 ns Package 400-mil 32-pin plastic TSOP II (TTP-32D)
HM62W8512BI Series
Pin Arrangement
32-pin TSOPII (Normal Type TSOP)
A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view)
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC A15 A17 WE A13 A8 A9 A11 OE A10 CS I/O7 I/O6 I/O5 I/O4 I/O3
Pin Description
Pin name A0 to A18 I/O0 to I/O7 CS OE WE VCC VSS Function Address input Data input/output Chip select Output enable Write enable Power supply Ground
2
HM62W8512BI...
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