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HM658512A Dataheets PDF



Part Number HM658512A
Manufacturers Hitachi Semiconductor
Logo Hitachi Semiconductor
Description 4 M PSRAM (512-kword x 8-bit) 2 k Refresh
Datasheet HM658512A DatasheetHM658512A Datasheet (PDF)

HM658512A Series 4 M PSRAM (512-kword × 8-bit) 2 k Refresh ADE-203-218C(Z) Rev. 3.0 Nov. 1997 Description The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. It offers low power data retention by self refresh mode. It also offers easy non multiplexed address interface and easy refresh functions. HM658512A is suitable for handy systems which work wit.

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HM658512A Series 4 M PSRAM (512-kword × 8-bit) 2 k Refresh ADE-203-218C(Z) Rev. 3.0 Nov. 1997 Description The Hitachi HM658512A is a CMOS pseudo static RAM organized 512-kword × 8-bit. It realizes higher density, higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. It offers low power data retention by self refresh mode. It also offers easy non multiplexed address interface and easy refresh functions. HM658512A is suitable for handy systems which work with battery back-up systems. The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 8 × 20 mm TSOP with thickness of 1.2 mm, or a 600-mil plastic DIP. High density custom cards made of Tape Carrier Packages are also available. Features • Single 5 V (±10%) • High speed  Access time CE access time: 70/80/100 ns (max)  Cycle time Random read/write cycle time: 115/130/160 ns (min) • Low power  Active: 250 mW (typ)  Standby: 200 µW (typ) • Directly TTL compatible All inputs and outputs • Simple address configuration Non multiplexed address • Refresh cycle  2048 refresh cycles: 32 ms HM658512A Series • Easy refresh functions Address refresh Automatic refresh Self refresh Ordering Information Type No. HM658512ALP-7 HM658512ALP-8 HM658512ALP-10 HM658512ALP-7V HM658512ALP-8V HM658512ALP-10V HM658512ALFP-7 HM658512ALFP-8 HM658512ALFP-10 HM658512ALFP-7V HM658512ALFP-8V HM658512ALFP-10V HM658512ALTT-7 HM658512ALTT-8 HM658512ALTT-10 HM658512ALTT-7V HM658512ALTT-8V HM658512ALTT-10V HM658512ALRR-7 HM658512ALRR-8 HM658512ALRR-10 HM658512ALRR-7V HM658512ALRR-8V HM658512ALRR-10V Access time 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 70 ns 80 ns 100 ns 400-mil 32-pin plastic TSOP (TTP-32DR) 400-mil 32-pin plastic TSOP (TTP-32D) 525-mil 32-pin plastic SOP (FP-32D) Package 600-mil 32-pin plastic DIP (DP-32) 2 HM658512A Series Pin Arrangement HM658512ALP/ALFP Series A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) HM658512ALTT Series A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 V CC A15 A17 WE A13 A8 A9 A11 OE/RFSH A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 VCC A15 A17 WE A13 A8 A9 A11 OE/RFSH A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 3 HM658512A Series Pin Arrangement (cont.) HM658512ALRR Series VCC A15 A17 WE A13 A8 A9 A11 OE/RFSH A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 (Top view) A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 VSS Pin Description Pin name A0 to A18 I/O0 to I/O7 CE OE/ RFSH WE VCC VSS Function Address Input/Output Chip enable Output enable/Refresh Write enable Power supply Ground 4 HM658512A Series Block Diagram A0 Address Latch Control Row Decoder Memory Matrix (2048 × 256) × 8 A10 Column I/O Column Decoder Address Latch Control I/O 0 I/O 7 Input Data Control A11 A18 Refresh Control CE OE/RFSH WE Timing Pulse Gen. Read Write Control 5 HM658512A Series Pin Functions CE: Chip Enable (Input) CE is a basic clock. RAM is active when CE is low, and is on standby when CE is high. A0 to A18: Address Inputs (Input) A0 to A10 are row addresses and A11 to A18 are column addresses. The entire addresses A0 to A18 are fetched into RAM by the falling edge of CE. OE/RFSH: Output Enable/Refresh (Input) This pin has two functions. Basically it works as OE when CE is low, and as RFSH when CE is high (in standby mode). After a read or write cycle finishes, refresh does not start if CE goes high while OE/RFSH is held low. In order to start a refresh in standby mode, OE/RFSH must go high to reset the refresh circuits of the RAM. After the refresh circuits are reset, the refresh starts when OE/RFSH goes low. I/O0 to I/O7: Input/Output (Inputs and Outputs) These pins are data I/O pins. WE : Write Enable (Input) RAM is in write mode when WE is low, and is in read mode when WE is high. I/O data is fetched into RAM by the rising edge of WE or CE (earlier timing) and the data is written into memory cells. Refresh There are three refresh modes : address refresh, automatic refresh and self refresh. (1) Address refresh: Data is refreshed by accessing all 2048 row addresses every 32 ms. A read is one method of accessing those addresses. Each row address (2048 addresses of A0 to A10)must be read at least once every 32 ms. In address refresh mode, OE/RFSH can remain high. In this case, the I/O pins remain at high impedance, but the refresh is done within RAM. (2) Automatic refresh: Instead of address refresh, automatic refresh can be used. RAM goes to automatic refresh mode if OE/RFSH falls while CE is high and it remains low for at least tFAP. One automatic refresh cycle is executed by one low pulse of OE/RFSH. It is not necessary to input the re.


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