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64k SRAM. HM9264B Datasheet |
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HM9264B Series
64 k SRAM (8-kword × 8-bit)
ADE-203-618C (Z)
Rev. 3.0
Nov. 1997
Description
The Hitachi HM9264B is 64k-bit static RAM organized 8-kword × 8-bit. It realizes higher performance
and low power consumption by 1.5 µm CMOS process technology. The device, packaged in 450 mil
SOP (foot print pitch width), 600 mil plastic DIP, is available for high density mounting.
Features
• High speed
Fast access time: 85/100 ns (max)
• Low power
Standby: 10 µW (typ)
Operation: 15 mW (typ) (f = 1 MHz)
• Single 5 V supply
• Completely static memory
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output
Three state output
• Directly TTL compatible
All inputs and outputs
• Battery backup operation capability
Note: HM9264B series can't be applied for Aerospace, Aircraft, Nucleus Plants, Main Flame
Computers, Medical Life-support System, and Automobile Engine Control and Industrial
machines. (e.g. Communication Hubs, NC, and others.)
Ordering Information
Type No.
HM9264BLFP-8L
HM9264BLFP-10L
HM9264BLP-8L
HM9264BLP-10L
Access time
85 ns
100 ns
85 ns
100 ns
Package
450-mil, 28-pin plastic SOP(FP-28DA)
600-mil, 28-pin plastic DIP (DP-28)
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HM9264B Series
Pin Arrangement
HM9264BLFP/BLP Series
NC 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O1 11
I/O2 12
I/O3
VSS
13
14
28 VCC
27 WE
26 CS2
25 A8
24 A9
23 A11
22 OE
21 A10
20 CS1
19 I/O8
18 I/O7
17 I/O6
16 I/O5
15 I/O4
(Top view)
Pin Description
Pin name
A0 to A12
I/O1 to I/O8
CS1
CS2
WE
OE
NC
VCC
VSS
Function
Address input
Data input/output
Chip select 1
Chip select 2
Write enable
Output enable
No connection
Power supply
Ground
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Block Diagram
A11
A8
A9
A7
A12
A5
A6
A4
I/O1
I/O8
CS2
CS1
WE
OE
HM9264B Series
Row
decoder
Memory array
256 × 256
VCC
VSS
Input
data
control
Column I/O
Column decoder
A1 A2 A0 A10 A3
Timing pulse generator
Read, Write control
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