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DTMF RECEIVER. HM9270D Datasheet

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DTMF RECEIVER. HM9270D Datasheet






HM9270D RECEIVER. Datasheet pdf. Equivalent




HM9270D RECEIVER. Datasheet pdf. Equivalent





Part

HM9270D

Description

DTMF RECEIVER



Feature


HM 9270C/D DTMF RECEIVER General Descri ption The HM 9270C/D is a complete DTMF receiver integrating both the bandspli t filter and digital decoder functions. The filter section uses switched capac itor techniques for high- and low-group filters and dial-tone rejection. Digit al counting techniques are employed in the decoder to detect and decode all 16 DTMF tonepairs in.
Manufacture

ELAN Microelectronics Corp

Datasheet
Download HM9270D Datasheet


ELAN Microelectronics Corp HM9270D

HM9270D; to a 4-bit code. External component coun t is minimized by on-chip provision of a differential input amplifier, clock-o scillator and latched 3-state bus inter face. Features • • • • • • • • Complete receiver in an 18-pin package. Excellent performance. CMOS, single 5 volt operation. Minimum board area. Central office quality. Low power consumption. Power-Down mode (HM9.


ELAN Microelectronics Corp HM9270D

270D only). Inhibit-mode (HM9270D only). Pin Configurations HM9270C IN+ IN GS 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD St/GT ESt StD Q4 Q3 Q2 Q1 TO E IN+ IN GS HM9270D 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 VDD St/GT ES t StD Q4 Q3 Q2 Q1 TOE VREF IC* IC* OSC 1 OSC2 VSS VREF INH PWDN OSC1 OSC2 VSS * Connect to VSS - 1 - HM 9270C/D D TMF RECEIVER Bloc.


ELAN Microelectronics Corp HM9270D

k Diagram (Figure 1) INH HIGH GROUP FIL TER IN+ IN DIGITAL ZERO CROSSING DETEC TORS DETECTION CODE CONVERTER AND Q1 Q2 Q3 Q4 + - DIAL TONE FILTER LOW GR OUP FILTER ALGORITHM LATCH GS CHIP CHIP CHIP CHIP CLOCKS POWER BIAS REF O SC2 BIAS CIRCUIT + STEERING LOGIC OSC1 VDD V SS PWDN VREF St/ GT ESt St D TOE Pin Description Pin 1 2 3 Sym. IN+ INGS Functio.

Part

HM9270D

Description

DTMF RECEIVER



Feature


HM 9270C/D DTMF RECEIVER General Descri ption The HM 9270C/D is a complete DTMF receiver integrating both the bandspli t filter and digital decoder functions. The filter section uses switched capac itor techniques for high- and low-group filters and dial-tone rejection. Digit al counting techniques are employed in the decoder to detect and decode all 16 DTMF tonepairs in.
Manufacture

ELAN Microelectronics Corp

Datasheet
Download HM9270D Datasheet




 HM9270D
HM 9270C/D
DTMF RECEIVER
General Description
The HM 9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder
functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone
rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tone-
pairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input
amplifier, clock-oscillator and latched 3-state bus interface.
Features
• Complete receiver in an 18-pin package.
• Excellent performance.
• CMOS, single 5 volt operation.
• Minimum board area.
• Central office quality.
• Low power consumption.
• Power-Down mode (HM9270D only).
• Inhibit-mode (HM9270D only).
Pin Configurations
HM9270C
IN+
IN
GS
VREF
IC*
IC*
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
9
18 VDD
17 St/GT
16 ESt
15 StD
14 Q4
13 Q3
12 Q2
11 Q1
10 TOE
HM9270D
IN+
IN
GS
VREF
INH
PWDN
OSC1
OSC2
VSS
1
2
3
4
5
6
7
8
9
18 VDD
17 St/GT
16 ESt
15 StD
14 Q4
13 Q3
12 Q2
11 Q1
10 TOE
* Connect to V
SS
-1-




 HM9270D
Block Diagram (Figure 1)
HM 9270C/D
DTMF RECEIVER
INH
IN+
IN
GS
OSC2
HIGH
DIGITAL
CODE
GROUP
FILTER ZERO
CROSSING
CONVERTER
+ DIAL
DETECTORS DETECTION
TONE
-
FILTER
LOW
AND
GROUP
FILTER
ALGORITHM
LATCH
CHIP CHIP CHIP CHIP
CLOCKS POWER BIAS REF
BIAS
CIRCUIT
+
-
STEERING
LOGIC
Q1
Q2
Q3
Q4
OSC1
VDDVSS PWDN
VREF St/ GT ESt
StD TOE
Pin Description
Pin Sym.
Function
1 IN+
2 IN-
Non-Inverting input
Invering Input
Connections to the front-end differential amplifier.
3 GS
Gain select. Gives access to output of front-end differential amplifier for connection of
feedback resistor.
4
VREF
Reference voltage output,nominally V /2. May be used to bias the inputs at midrail (see
DD
application diagram).
5 INH Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down resistor.
(HM9270D only).
6 PWDN Power down (input). Active high power down the device and inhibit the oscillator internal
built-in pull down resistor. (HM9270D only).
7 OSC1 Clock Input
8 OSC2 Output
3.579545 MHz crystal connected between these pins completCeslock
internal oscillator.
9V
SS
Negative power supply, normally connected to 0V.
10 TOE 3-state data output enable (input). Logic high enables the outputs Q1-Q4. Internal pull-up.
-2-




 HM9270D
HM 9270C/D
DTMF RECEIVER
Pin Sym.
11 Q1
12 Q2
13 Q3
14 Q4
Function
3-state data outputs. When enabled by TOE, provide the code corresponding to the last valid
tone-pair received (see code table).
15 StD Delayed steering output. Presents a logic high when a received tone-pair has been registered
and the output latch updated; returns to logic low when the voltage on St/GT falls below
V.
TSt
16 ESt Early steering output. Presents a logic high immediately when the digital algorithm detects a
recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause
ESt to return to a logic low.
17 St/GT Steering input/guard time output (bi-directional). A voltage greater than VTSt detected at St
causes the device to register the detected tone-pair and update the output latch. A voltage
less than V frees the device to accept a new tone-pair. The GT output acts to reset the
TSt
external steering time-constant; its state is a function of ESt and the voltage on St (see truth
table).
18 V
Positive power supply, +5Volts.
DD
Absolute Maximum Ratings (Notes 1, 2 and 3)
Parameters
Min.
Max.
Units
Power Supply Voltage, V - V
DD SS
Voltage on any pin
Current at any pin
V - 0.3
SS
6
V + 0.3
DD
10
V
V
mA
Operating temperature
-40 +85 oC
Storage temperature
-65
+150
oC
Package power dissipation
500 mW
Note 1. Absolute maximum ratings are those values beyond which damage to the device may
occur.
2. Unless otherwise specified, all voltages are referenced to ground.
3.
Power
dissipation
temperature
derating:
-12
/mV
oC
from
65oC
to
85oC
DC Electrical Characteristics
Parameter Description
SUPPLY:
VDD
I
cc
P
o
IS
Operating Supply Voltage
Operating Supply Current
Power Consumption
Standby Current
INPUTS:
VIL
VIH
I /I
IH IL
I
so
R
IN
VTSt
Low Level Input Voltage
High Level Input Voltage
Input Leakage Current
Pull Up (Source) Current
Input
Signal
Impedance Inputs 1,2
Steering Threshold Voltage
Test Conditions
f=3.579MHz; V =5V
DD
PWDN pin = V
DD
V =V or V
IN ss
DD
TOE (Pin 10)=OV
@ 1kHz
-3-
Min. Typ. Max. Units
4.75
3.0
15
--
5.25
7
35
100
V
mA
mW
µA
1.5
3.5
0.1
7.5 15
10
2.35
V
V
uA
uA
M
V



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