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Chip Microcomputer. CXP82900 Datasheet |
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CXP82900
CMOS 8-bit Single Chip Microcomputer
Piggyback/
evaluator type
Description
The CXP82900 is a CMOS 8-bit single chip micro-
computer of piggyback/evaluator combined type,
which is developed for evaluating the function of the
CXP82940/82948/82952/82960.
80 pin PQFP (Ceramic)
Features
• Wide-range instruction system (213 instructions)
to cover various types of data
— 16-bit operation/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation
122µs at 32kHz operation
• Applicable EPROM
LCC type 27C512 (Maximum 60K bytes are available.)
• Incorporated RAM capacity 2048 bytes (Including fluorescent display data area.)
• Peripheral functions
— A/D converter
8-bit, 8-channel, successive approximation method
(Conversion time of 20µs/16MHz)
— Serial interface
Incorporated buffer RAM (Auto transfer for 1 to 32bytes), 1 channel
Incorporated 8-bit, 8-stage FIFO (Auto transfer for 1 to 8 bytes), 1 channel
— Timer
8-bit timer
8-bit timer/counter
19-bit time base timer
32kHz timer/counter
— Fluorescent display panel controller/driver
Maximum 196-segment display possible
1 to 16-digit dynamic display
Dimmer function
High voltage drive output (40V)
Pull-down function
Hardware key scan function (Maximum 12 × 8 key matrix compatible)
— I2C bus interface
— Remote control transmission circuit
Auto transmission for 1 to 32 bytes, restart function, carrier output function
— Remote control reception circuit
8-bit pulse measurement counter with on-chip 6-stage FIFO
• Interruption
16 factors, 15 vectors, multi-interruption possible
• Standby mode
SLEEP/STOP
• Package
80-pin ceramic QFP
Note) Mask option depends on the type of the CXP82900. Refer to the Products List for details.
Structure
Silicon gate CMOS IC
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E95613-PP
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Pin Configuration in Piggyback Mode
CXP82900
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5
PE6/RMCO
PE7/TO/ADJ
PB0
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
AVDD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1 64
2 63
3 62
4 61
5 60
6 59
7 58
8 4 3 2 1 32 31 30 57
9 A6 5
29 A8
56
10 A5 6
28 A9
55
11 A4 7
27 A11
54
12 A3 8
26 NC
53
13 A2 9
25 OE
52
14 A1 10
24 A10
51
15 A0 11
23 CE
50
16 NC 12
22 D7
49
17 D0 13
21 D6
48
18 14 15 16 17 18 19 20
47
19 46
20 45
21 44
22 43
23 42
24 41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
T7
T8/S19
T9/S18
T10/S17
T11/S16
T12/S15
T13/S14
T14/S13
T15/S12
S11
S10
S9
S8
PD7/S7
PD6/S6
PD5/S5
PD4/S4
PD3/S3
PD2/S2
PD1/S1
PD0/S0
VFDP
PC7/KR7
PC6/KR6
Note) NC (Pin 75) is always connected to VDD.
–2–
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Pin Configuration in Evaluator Mode
CXP82900
PE1/INT1
PE2/INT2
PE3/INT3/NMI
PE4/RMC
PE5
PE6/RMCO
PE7/TO/ADJ
PB0
PB1/CS0
PB2/SCK0
PB3/SI0
PB4/SO0
PB5/SCK1
PB6/SI1
PB7/SO1
PA0/AN0
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
AVDD
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
1
2
3
4
5
6
7
8
9 A6/D6
10 A5/D5
11 A4/D4
12 A3/D3
13 A2/D2
14 A1/D1
15 A0/D0
16 NC
17 RD
18
19
20
21
22
23
24
4 3 2 1 32 31 30
5 29
6 28
7 27
8 26
9 25
10 24
11 23
12 22
13 21
14 15 16 17 18 19 20
A8
A9
A11
NC
HALT
A10
E/P
I/T
MON
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
T7
T8/S19
T9/S18
T10/S17
T11/S16
T12/S15
T13/S14
T14/S13
T15/S12
S11
S10
S9
S8
PD7/S7
PD6/S6
PD5/S5
PD4/S4
PD3/S3
PD2/S2
PD1/S1
PD0/S0
VFDP
PC7/KR7
PC6/KR6
Note) NC (Pin 75) is always connected to VDD.
–3–
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