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CY28324 Dataheets PDF



Part Number CY28324
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description FTG for Intel Pentium 4 CPU and Chipsets
Datasheet CY28324 DatasheetCY28324 Datasheet (PDF)

PRELIMINARY CY28324 FTG for Intel® Pentium® 4 CPU and Chipsets Features • Compatible to Intel CK-00, CK-Titan & CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel 850, Brookdale (845) and Brookdale - G Pentium® 4 Chipsets • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog Timer for system recovery • Automatically switch to HW selected or SW programmed clock frequency when Watchdog Timer time-out • Capable of.

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PRELIMINARY CY28324 FTG for Intel® Pentium® 4 CPU and Chipsets Features • Compatible to Intel CK-00, CK-Titan & CK-408 Clock Synthesizer/Driver Specifications • System frequency synthesizer for Intel 850, Brookdale (845) and Brookdale - G Pentium® 4 Chipsets • Programmable clock output frequency with less than 1 MHz increment • Integrated fail-safe Watchdog Timer for system recovery • Automatically switch to HW selected or SW programmed clock frequency when Watchdog Timer time-out • Capable of generating system RESET after a Watchdog Timer time-out occurs or a change in output frequency via SMBus interface ® • Support SMBus byte read/write and block read/write operations to simplify system BIOS development • Vendor ID and Revision ID support • Programmable drive strength support • Programmable output skew support • Power management control inputs • Available in 48-pin SSOP CPU x2 3V66 x4 PCI x 10 REF x2 48M x1 24_48M x1 Block Diagram X1 X2 Pin Configuration VDD_REF REF0:1 XTAL OSC PLL 1 SSOP-48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/MULTSEL0* GND_REF VDD_MREF 3VMREF/CPU_STP#* 3VMREF#/PCI_STP#* GND_MREF PWR_DWN# CPU0 CPU0# VDD_CPU CPU1 CPU1# GND_CPU IREF VDD_CORE GND_CORE VDD_3V66 3V66_0 3V66_1 GND_3V66 3V66_2 3V66_3 SCLK SDATA PLL Ref Freq Divider Network Stop Clock Control *FS0:4 VTT_PWRGD# *CPU_STP# *MULTSEL0:1 PWR_DWN# Stop Clock Control *PCI_STP# *MULTSEL1/REF1 VDD_REF X1 X2 GND_PCI *FS2/PCI_F0 *FS3/PCI_F1 VDD_MREF 3VMREF, 3VMREF# *MODE/PCI_F2 VDD_PCI VDD_3V66 *FS4/PCI0 3V66_0:3 PCI1 PCI2 GND_PCI VDD_PCI PCI3 PCI_F0:2 PCI4 PCI0:6 PCI5 PCI6 VDD_PCI VTT_PWRGD# RST# GND_48MHz *FS0/48MHz *FS1/24_48MHz VDD_48MHz VDD_48MHz VDD_CPU CPU0:1, CPU0:1# 48MHz ~ CY28324 PLL2 24_48MHz 2 Note: 1. Signals marked with ‘*’ have internal pull-up resistor. SDATA SCLK SMBus Logic RST# Intel and Pentium are registered trademarks of Intel Corporation. Cypress Semiconductor Corporation Document #: 38-07002 Rev. *A • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised November 14, 2001 PRELIMINARY Pin Definitions Pin Name X1 Pin No. 3 Pin Type I Pin Description CY28324 Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. Crystal Connection: Connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = IOH is 4 x IREF 01 = IOH is 5 x IREF 10 = IOH is 6 x IREF 11 = IOH is 7 x IREF Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz clock output. This pin also serves as a power-on strap option to determine the current multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows: MULTSEL1:0 00 = Ioh is 4 x IREF 01 = IOH is 5 x IREF 10 = IOH is 6 x IREF 11 = IOH is 7 x IREF CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through the serial input interface. Memory Reference Clock/CPU Output Control: The function of this pin is controlled by the Mode input pin. When Mode input is sampled HIGH during power-on reset, this pin will be configured as 3VMREF output. When Mode input is sampled LOW during power-on reset, this pin will be configured as CPU_STP# input. 3VMREF is a 3.3V output running at half the frequency of the CPU output clock. CPU_STP# is a 3.3V LVTTL compatible input that disables CPU0, CPU0#, CPU1 and CPU1# outputs. Memory Reference Clock/PCI Output Control: The function of this pin is controlled by the Mode input pin. When Mode input is sampled HIGH during power-on reset, this pin will be configured as 3VMREF# output. When Mode input is sampled LOW during power-on reset, this pin will be configured as PCI_STP# input. 3VMREF# is a 3.3V output running at half the frequency of the CPU output clock. 3VMREF# is 180 degree out of phase with respect to 3VMREF. PCI_STP# is a 3.3V LVTTL-compatible input that disables PCI0:6 outputs. 66-MHz Clock Outputs: 3.3V fixed 66-MHz clock. Free-running PCI Output 0/Frequency Select 2: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. Free-running PCI Output 1/Frequency Select 3: 3.3V free-running PCI output. This pin also serves as a power-on strap option to determine device operating frequency as described in the Frequency Selection Table. X2 REF0/MULTSEL0 4 48 O I/O REF1/MULTSEL1 1 I/O CPU0:1, CPU0:1# 3VMREF/CPU_STP # 41, 38, 40, 37 45 O I/O 3VMREF#/PCI_STP # 44 I/O 3V66_0:3 PCI_F0/FS2 31, 30, 28, 27 6 O I/O PCI_F1/FS3 7 I/O Document #:.


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