CY28343

CY28343 Zero Delay SDR/DDR Clock Buffer Features Phase-lock loop clock distribution for DDR and SDR SDRAM applications One-single-end clock input to 6 pairs DDR outputs or 13 SDR outputs. External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for SDR. Table 1. Function Table SELDDR_SDR# 1= DDR Mode CLKIN 2.5V Compatible 3.3V Compatible SDRAM(0:12) OFF DDRT/C(0:5) Active 2.5V Compatible OFF FBIN_DDR 2.5V Compatible OFF FBOUT_DDR Active 2.5V Compatible OFF FBIN_SDR FBOUT_SDR OFF OFF External feedback pins FBIN_SDR/FBOUT_SDR are used to synchronize the outputs to the clock input for DDR. SMBus interface enables/disables outputs. Conforms to JEDEC SDR/DDR specifications Low jitter, low skew 48 pin SSOP package 0 = SDRAM Mode Active 3.3V Compatible Active 3.3V Compatible Active 3.3V Compatible Block Diagram Pin Configuration[1] SCLK SDATA Control Logic VDD_2.5V FBOUT_DDR VDD_3.3V DDRT(0:5) DDRC(0:5) CLKIN FBIN_DDR VDD_3.3V FBOUT_SDR PLL *SELDDR_SDR FBIN_SDR SDRAM (0:12) VDD_3.3V SDRAM0 SDRAM1 SDRAM2 SDRAM3 VSS VDD_3.3V SDRAM4 SDRAM5 CLKIN SDRAM6 SDRAM7 VSS VDD_3.3V SDRAM8 SDRAM9 SDRAM10 SDRAM11 VSS VDD_3.3V SDRAM12 FBOUT_SDR FBIN_SDR* VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 SELDDR_SDR#* FBIN_DDR* FBOUT_DDR VDD_2.5V DDRT5 DDRC5 DDRT4 DDRC4 VSS VDD_2.5 DDRT3 DDRC3 DDRT2 DDRC2 VSS VDD_2.5V DDRT1 DDRC1 DDRT0 DDRC0 ...