| DatasheetsPDF.com |
CY37032P44-154JI Datasheet, Equivalent, High-Performance CPLDs.5V/ 3.3V/ ISR High-Performance CPLDs 5V/ 3.3V/ ISR High-Performance CPLDs |
| Part | CY37032P44-154JI |
|---|---|
| Description | 5V/ 3.3V/ ISR High-Performance CPLDs |
| Feature | Ultra37000 CPLD Family
5V, 3. 3V, ISR™ High-Performance CPLDs Features • In -System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigu rability — Design changes do not caus e pinout changes — Design changes do not cause timing changes • High densi ty — 32 to 512 macrocells — 32 to 2 64 I/O pins — Five dedicated inputs i ncluding four clock pins • Simple tim ing model — No fanout delays — No e xpander delays — No dedicated vs. I/O pin delays — No additional delay thr ough PIM — No penalty for using full 16 product terms • • • • — No delay for steering or sharing product terms 3. 3V and 5V v . |
| Manufacture | Cypress Semiconductor |
| Datasheet |
| Part | CY37032P44-154JI |
|---|---|
| Description | 5V/ 3.3V/ ISR High-Performance CPLDs |
| Feature | Ultra37000 CPLD Family
5V, 3. 3V, ISR™ High-Performance CPLDs Features • In -System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigu rability — Design changes do not caus e pinout changes — Design changes do not cause timing changes • High densi ty — 32 to 512 macrocells — 32 to 2 64 I/O pins — Five dedicated inputs i ncluding four clock pins • Simple tim ing model — No fanout delays — No e xpander delays — No dedicated vs. I/O pin delays — No additional delay thr ough PIM — No penalty for using full 16 product terms • • • • — No delay for steering or sharing product terms 3. 3V and 5V v . |
| Manufacture | Cypress Semiconductor |
| Datasheet |
| @ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact) |