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CY37064P84-125JC Datasheet, Equivalent, High-Performance CPLDs.5V/ 3.3V/ ISR High-Performance CPLDs 5V/ 3.3V/ ISR High-Performance CPLDs |
| Part | CY37064P84-125JC |
|---|---|
| Description | 5V/ 3.3V/ ISR High-Performance CPLDs |
| Feature | Ultra37000 CPLD Family
5V, 3. 3V, ISR™ High-Performance CPLDs Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays — No additional delay through PIM — No penalty for using full 16 product terms • • • • — No delay for steering or sharing product terms 3. 3V and 5V v. |
| Manufacture | Cypress Semiconductor |
| Datasheet |
| Part | CY37064P84-125JC |
|---|---|
| Description | 5V/ 3.3V/ ISR High-Performance CPLDs |
| Feature | Ultra37000 CPLD Family
5V, 3. 3V, ISR™ High-Performance CPLDs Features • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays — No additional delay through PIM — No penalty for using full 16 product terms • • • • — No delay for steering or sharing product terms 3. 3V and 5V v. |
| Manufacture | Cypress Semiconductor |
| Datasheet |
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