CY37512 | Cypress Semiconductor
5V/ 3.3V/ ISR High-Performance CPLDs
Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No.
- CY37512 | Cypress Semiconductor
- 5V/ 3.3V/ ISR High-Performance CPLDs
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (.
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays.
- CY37512P208-100NC | Cypress Semiconductor
- 5V/ 3.3V/ ISR High-Performance CPLDs
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (.
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays.
- CY37512P208-100NI | Cypress Semiconductor
- 5V/ 3.3V/ ISR High-Performance CPLDs
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (.
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays.
- CY37512P208-125NC | Cypress Semiconductor
- 5V/ 3.3V/ ISR High-Performance CPLDs
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (.
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays.
- CY37512P208-83NC | Cypress Semiconductor
- 5V/ 3.3V/ ISR High-Performance CPLDs
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (.
- Ultra37000 CPLD Family
5V, 3.3V, ISR™ High-Performance CPLDs
Features
• In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated inputs including four clock pins • Simple timing model — No fanout delays — No expander delays — No dedicated vs. I/O pin delays.
