CY6117A-45LMB

6116A: 11/8/89 Revision: Monday, November 8, 1993 Features D D D D D D D Automatic powerĆdown when deselected CMOS for optimum speed/power High speed Ċ 20 ns Low active power Ċ 550 mW Low standby power Ċ 110 mW TTLĆcompatible inputs and outputs Capable of withstanding greater than 2001V electrostatic discharge The CY6116A and CY6117A are highĆ performance CMOS static RAMs orgaĆ nized as 2048 words by 8 bits. Easy memoryexpansionisprovidedbyanactive LOW chip enable (CE) and active LOW output enable (OE), and threeĆstate drivĆ ers. The CY6116A and CY6117A have an automatic powerĆdown feature, reducing the power consumption by 83% when deĆ selected. Writingtothedeviceisaccomplishedwhen the chip enable (CE) and write enable (WE) inputs are both LOW. Data on the I/Opins(I/O0 throughI/O7)iswritteninto Functional Description the memory location specified on the adĆ dress pins (A0 through A10). ReadingthedeviceisaccomplishedbytakĆ ing chip enable (CE) and output enable (OE) LOW while write enable (WE) reĆ mainsHIGH.Undertheseconditions,the contents of the memory location specified on the address pins will appear on the I/O pins. The I/O pins remain in highĆimpedance state when chip enable (CE) is HIGH or write enable (WE) is LOW. The CY6116A and CY6117A utilize a die coat to insure alpha immunity. 2K x 8 Static RAM CY6116A CY6117A Logic Block Diagram A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 6116A Pin Configurations DIP/SOJ Top View 24 23 22 21 20 19 18 17 16 15 14 13 ...