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Part Number AN805
Manufacturers Vishay Siliconix
Logo Vishay Siliconix
Description PWM Optimized Power MOSFET
Datasheet AN805 DatasheetAN805 Datasheet (PDF)

AN805 Vishay Siliconix PWM Optimized Power MOSFETs for Low-Voltage DC/DC Conversion Designers of low-voltage dc-to-dc converters have two main concerns: reducing size and reducing losses. As a way of reducing size, designers are increasing switching frequencies. But the result has been reduced converter efficiency. To minimize losses, MOSFET manufacturers have generally focused on lowering on-resistance. But the results have not been optimal for dc-to-dc conversion designs, since gate charge an.

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AN805 Vishay Siliconix PWM Optimized Power MOSFETs for Low-Voltage DC/DC Conversion Designers of low-voltage dc-to-dc converters have two main concerns: reducing size and reducing losses. As a way of reducing size, designers are increasing switching frequencies. But the result has been reduced converter efficiency. To minimize losses, MOSFET manufacturers have generally focused on lowering on-resistance. But the results have not been optimal for dc-to-dc conversion designs, since gate charge and switching speed issues have been largely ignored. The dominant losses associated with MOSFETs were once conduction losses, but this is no longer the case. Vishay Siliconix’s new family of PWM optimized MOSFETs has been designed to give the highest efficiency available for a given on-resistance in switching applications such as dc-to-dc conversion. These new devices provide a very low gate charge per unit of on-resistance, in addition to fast switching times. The result is reduced gate drive and crossover losses, allowing designers of dc-to-dc converters to simultaneously reduce the design footprint and increase efficiency. MOSFET Losses A simplistic model of power loss in a MOSFET used in a dc-to-dc converter (Figure 1) can be calculated if we know the RMS, the current through the MOSFET, the duty cycle, the gate voltage, and the rDS(on) of the MOSFET. This model can then be used to compare the efficiency of designs using Vishay Siliconix’s new PWM optimized MOSFETs versus conventional and low-threshold power MOSFETs. The equation that defines the losses associated only with on-resistance and the gate drive is: P + I 2RMS D ) Q [ ] The value of the parameter before the parenthesis is dependent on the parameter within the parenthesis. Drain IRMS Crss RG Gate Ciss rDS(on) Coss Source FIGURE 1. Generic MOSFET model with body diode omitted. where: I2RMS rDS(on) VGS [TJ] D Qg f The RMS current in the MOSFET (A) On-resistance of the device for a given drive voltage and junction temperature. The peak driver gate voltage for the MOSFET (V) Junction temperature of the MOSFET Duty factor of the MOSFET (Ratio of on time to off time) Total gate charge for the MOSFET at a given gate voltage (C) Frequency of MOSFET switching (Hz) r DS(on) ƪVGSƫ ƪT Jƫ f (Watts) Eq1 g V ƪ GS ƫ VGS Using Equation 1 we can obtain a plot of power loss (gate loss + rDS(on) loss) as a function of gate voltage at varying switching frequencies (Figure 2). [1] Technology Comparison: 1 MHz Power Loss 0.8 0.6 r DS(on) ( W ) Conduction + Gate Charge 50 Si6801 Power Loss, QG, rDS VGS 40 Gate Charge (nC) 30 Power Loss (mW) 40 30 40 Loss (mW) 20 10 0 20 10 0 0 1 2 3 V GS 4 5 6 7 0.4 0.2 30 20 0 10 1 2 3 V GS 4 5 6 7 FIGURE 2. Power loss for PWM optimized Si6801 p-channel MOSFET as a function of VGS and switching frequency. FIGURE 3. Gate losses and on-resistance losses for PWM optimized power MOSFET (Si6801DQ) versus conventional (Si6542DQ) and low-threshold (Si6552DQ) power MOSFETs. www.vishay.com S FaxBack 408-970-5600 Document Number: 70649 January 1997 1 AN805 Vishay Siliconix Figure 2 shows the respective contribution of on-resistance and gate charge to overall losses for the p-channel Si6801DQ at three different switching frequencies. At low gate-source voltages, the rDS(on) of the MOSFET is high and therefore on-resistance losses dominate. At higher gate-source voltages, on-resistance becomes almost a constant and the gate charge losses controlled by Qg dominate. Gate losses increase with the switching frequency, causing a narrowing in the optimum gate voltage. Therefore, the optimum drive voltage will be at a level which is just enough to take the rDS(on) into its constant region, but no further. Typically, this drive voltage is between 3 and 5 V, which is what most controller ICs provide. Figure 3 compares the power losses, at a switching frequency of 1 MHz, of Vishay Siliconix’s PWM optimized Si6801DQ, a conventional power MOSFET (Si6542DQ), and a low-threshold power MOSFET (Si6552DQ). Power losses for the PWM optimized MOSFET at gate drives between 2.5 and 5.5 V are significantly lower than both conventional and low-threshold MOSFETs, making the optimized device the obvious choice for all switching applications.[7.] The PWM Optimized MOSFET in a Real Application The PWM optimized power MOSFET is best viewed in the context of a real application. In the example used here, the Si6801DQ is paired with the Si9160BQ switching regulator IC to create a synchronous boost converter for cellular telephones with the following specifications: Input voltage: 2.7 V to 5 V (single-cell lithium ion battery is 2.7 V to 4.2 V) Output voltage: 5V Output current: 1 A maximum Gate drive voltage: 4.5 V Control scheme: Constant frequency voltage mode control Switching frequency: Varied by RC value from 300 kHz to 1.8 MHz All results shown are with VIN = 3.6 V, VOUT = 5 V, IOUT = 600 mA, f = 1 MHz unless otherwise stated. 1-Cell LiIon D1.


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