AN925

AN925 APPLICATION NOTE Time Update in ST’s TIMEKEEPER Devices Figure 1 shows how the non-volatile, static memory array and the quartz controlled clock oscillator, of TIMEKEEPER devices from STMicroelectronics, are interconnected through the clock registers. The clock registers are mapped into the memory array (please see the data sheet for the precise mapping) as 8 or 16 BYTEWIDE BIPORT memory cells. The time data in these memory cells are updated from the clock side (the system side) and are made available to the user side within the user’s finest time resolution. However, the user’s finest time resolution is one second, so this leaves plenty of scope for variability (of the order of several milliseconds) between one update and the next. Since this variability might be noticeable to some applications (for example, those that poll the time registers regularly, or those that use an alarm function that is triggered once per second), this document sets out to explain the nature of the variability, to make it more predictable to the applications designer. Figure 1. Internal Architecture of an ST TIMEKEEPER Device WDI INTEGRATED BATTERY CRYSTAL AND SNAPHAT OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL 8, 16 x 8 TIMEKEEPER REGISTERS POWER BATTERY LOW LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY SRAM ARRAY A0-AX DQ0-DQ7 E VPFD W G VCC IRQ/FT RST VSS AI02482 December 1998 1/4 AN925 - APPLICATION NOTE A 1 Hz clock signal, from the clock chain, is used to update th...