Document
FINAL
Am79C940
Media Access Controller for Ethernet (MACETM)
DISTINCTIVE CHARACTERISTICS
s s s s Integrated Controller with 10BASE-T transceiver and AUI port Supports IEEE 802.3/ANSI 8802-3 and Ethernet standards 84-pin PLCC and 100-pin PQFP Packages 80-pin Thin Quad Flat Pack (TQFP) package available for space critical applications such as PCMCIA Modular architecture allows easy tuning to specific applications High speed, 16-bit synchronous host system interface with 2 or 3 cycles/transfer Individual transmit (136 byte) and receive (128 byte) FlFOs provide increase of system latency and support the following features: – Automatic retransmission with no FIFO reload – Automatic receive stripping and transmit padding (individually programmable) – Automatic runt packet rejection – Automatic deletion of collision frames – Automatic retransmission with no FIFO reload s Direct slave access to all on board configuration/status registers and transmit/ receive FlFOs Direct FIFO read/write access for simple interface to DMA controllers or l/O processors s s s s s
Advanced Micro Devices
s
s s s
s s
s
Arbitrary byte alignment and little/big endian memory interface supported Internal/external loopback capabilities External Address Detection Interface (EADI™) for external hardware address filtering in bridge/router applications JTAG Boundary Scan (IEEE 1149.1 ) test access port interface for board level production test Integrated Manchester Encoder/Decoder Digital Attachment Interface (DAI™) allows by-passing of differential Attachment Unit Interface (AUI) Supports the following types of network interface: – AUI to external 10BASE2, 10BASE5 or 10BASE-F MAU – DAI port to external 10BASE2, 10BASE5, 10BASE-T, 10BASE-F MAU – General Purpose Serial Interface (GPSI) to external encoding/decoding scheme – Internal 10BASE-T transceiver with automatic selection of 10BASE-T or AUI port Sleep mode allows reduced power consumption for critical battery powered applications 1 MHz – 25 MHz system clock speed
s
GENERAL DESCRIPTION
The Media Access Controller for Ethernet (MACE) chip is a CMOS VLSI device designed to provide flexibility in customized LAN design. The MACE device is specifically designed to address applications where multiple I/O peripherals are present, and a centralized or system specific DMA is required. The high speed, 16-bit synchronous system interface is optimized for an external DMA or I/O processor system, and is similar to many existing peripheral devices, such as SCSI and serial link controllers. The MACE device is a slave register based peripheral. All transfers to and from the system are performed using simple memory or I/O read and write commands. In conjunction with a user defined DMA engine, the MACE chip provides an IEEE 802.3 interface tailored to a specific application. Its superior modular architecture and versatile system interface allow the MACE device to be configured as a stand-alone device or as a connectivity cell incorporated .