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MIC59P50 Dataheets PDF



Part Number MIC59P50
Manufacturers Micrel Semiconductor
Logo Micrel Semiconductor
Description 8-Bit Parallel-Input Protected Latched Driver
Datasheet MIC59P50 DatasheetMIC59P50 Datasheet (PDF)

MIC59P50 Micrel MIC59P50 8-Bit Parallel-Input Protected Latched Driver General Description The MIC59P50 parallel-input latched driver is a high-voltage (80V), high-current (500mA) integrated circuit comprised of eight CMOS data latches, a bipolar Darlington transistor driver for each latch, and CMOS control circuitry for the common CLEAR, STROBE, and OUTPUT ENABLE functions. Similar to the MIC5801, additional protection circuitry supplied on this device includes thermal shutdown, under voltag.

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MIC59P50 Micrel MIC59P50 8-Bit Parallel-Input Protected Latched Driver General Description The MIC59P50 parallel-input latched driver is a high-voltage (80V), high-current (500mA) integrated circuit comprised of eight CMOS data latches, a bipolar Darlington transistor driver for each latch, and CMOS control circuitry for the common CLEAR, STROBE, and OUTPUT ENABLE functions. Similar to the MIC5801, additional protection circuitry supplied on this device includes thermal shutdown, under voltage lockout (UVLO), and over-current shutdown. The bipolar/MOS combination provides an extremely lowpower latch with maximum interface flexibility. The MIC59P50 has open-collector outputs capable of sinking 500mA and integral diodes for inductive load transient suppression with a minimum output breakdown voltage rating of 80V above VEE (50V sustaining). The drivers can be operated with a split supply, where the negative supply is down to –20V and may be paralleled for higher load current capability. With a 5V logic supply, the MIC59P50 will typically operate at better than 5MHz. With a 12V logic supply, significantly higher speeds are obtained. The CMOS inputs are compatible with standard CMOS, PMOS, and NMOS circuits. TTL circuits may require pull-up resistors. Each of these eight outputs has an independent over-current shutdown at 500 mA. Upon current shutdown, the affected channel will turn OFF and the flag will go low until VDD is cycled or the ENABLE/RESET pin is pulsed high. Current pulses less than 2µs will not activate over-current shutdown. Temperatures above 165°C will shut down the device and activate the open collector FLAG output at pin 1. The UVLO circuit disables the outputs at low VDD; hysteresis of 0.5V is provided. Features • • • • • • • • • • • 4.4 MHz Minimum Data Input Rate High-Voltage, High-Current Outputs Per-Output Over-Current Shutdown (500mA Typical) Undervoltage Lockout Thermal Shutdown Output Fault Flag Output Transient Protection Diodes CMOS, PMOS, NMOS, and TTL Compatible Inputs Internal Pull-Down Resistors Low-Power CMOS Latches Single or Split Supply Operation Ordering Information Part Number MIC59P50BN MIC59P50BV MIC59P50BWM * 300-mil “skinny DIP” Temperature Range –40°C to +85°C –40°C to +85°C –40°C to +85°C Package 24-Pin Plastic DIP* 28-Pin PLCC 24-Pin Wide SOIC Functional Diagram STROBE V DD CLEAR FLAG ENABLE/RESET Pin Configuration (DIP and SOIC) ISHUTDOWN – + IREF IOUT / N FLAG CLEAR STROBE 1 2 3 4 5 6 THERMAL SHUTDOWN ILIMIT 24 VSS 23 OUTPUT ENABLE/RESET 22 VDD 21 OUT 1 20 OUT 2 19 OUT 3 2.2R + – UVLO THERMAL SHUTDOWN S R Q OUTPUT COMMON 1.25V R IN 1 IN 2 IN 3 LATCHES IN IN 4 R1 70k 7 8 9 18 OUT 4 17 OUT 5 16 OUT 6 15 OUT 7 14 OUT 8 UVLO 13 COMMON IN 5 R2 3k Circuitry below dashed line is included in each of the 8 channels. V EE IN 6 IN 7 10 IN 8 11 VEE 12 7-58 October 1998 MIC59P50 Micrel Absolute Maximum Ratings TA = +25°C Output Voltage (VCE) .................................................... 80V Supply Voltage (VDD) .................................................... 15V (VDD – VEE) ............................................................... 25V Input Voltage (VIN) ............................... –0.3V to VDD+0.3V Continuous Collector Current (IC) ............................ 500mA Protected Current ............................................ 1.5A, Note 1 Power Dissipation (PD) Plastic DIP (N) ......................................................... 2.4W Derate above TA = +25°C ............................24mW/°C PLCC (V) ................................................................. 1.6W Derate above TA = +25°C ............................16mW/°C Wide SOIC (WM) .................................................... 1.4W Derate above TA = +25°C ............................14mW/°C Operating Temperature (TA) Plastic DIP (N), PLCC (V), SOIC (WM) .. –40°C to +85°C Storage Temperature (TS) ....................... –65°C to +150°C Junction Temperature (TJ) ...................................... +150°C ESD ......................................................................... Note 2 Note 1: Note 2: Each channel. VEE connection must be designed to minimize inductance and resistance. Devices are input-static protected but can be damage by extremely high static charges. PLCC Pin Configuration OE/RESET 27 STROBE CLEAR FLAG 4 3 2 1 28 VDD 26 25 24 23 VEE VSS IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 5 6 7 8 9 10 11 12 13 14 15 16 17 18 OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 MIC59P50BV 22 21 20 19 COMMON Allowable Output Current ALLOWABLE COLLECTOR CURRENT IN mA AT 50°C MIC59P50BN 450 400 350 300 250 200 150 100 0 NUMBER OF OUTPUTS CONDUCTING SIMULTANEOUSLY 10 20 30 40 50 60 70 80 90 100 6 7 8 4 5 3 1 or 2 Typical Input V DD OUT 8 NC IN 8 NC VEE NC IN 7 PERCENT DUTY CYCLE Pin Description Pin 1 Name FLAG Description Error Flag. Open Collector Output is Low upon Overcurrent Fault or Overtemperature Fault. OUTPUT ENABLE/RES.


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