Sync FIFOs. CY7C4291 Datasheet
64K/128K x 9 Deep Sync FIFOs
• High-speed, low-power, first-in first-out (FIFO)
• 64K × 9 (CY7C4281)
• 128K × 9 (CY7C4291)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
• Low power
— ICC= 40 mA
— ISB = 2 mA
• Fully asynchronous and simultaneous read and write
• Empty, Full, and programmable Almost Empty and
Almost Full status flags
• TTL compatible
• Output Enable (OE) pin
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width Expansion Capability
• 32-pin PLCC
• Pin-compatible density upgrade to CY7C42X1
• Pin-compatible density upgrade to
Logic Block Diagram
D0 − 8
The CY7C4281/91 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4281/91 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high-speed data acquisition, multiprocessor inter-
faces, and communications buffering.
These FIFOs have nine-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the
CY7C4281/91 has an output enable pin (OE). The read
(RCLK) and write (WCLK) clocks may be tied together for
single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock
frequencies up to 100 MHz are achievable. Depth expansion
is possible using one enable input for system control, while the
other enable is controlled by expansion logic to direct the flow
WCLK WEN1 WEN2/LD
64K x 9
128K x 9
4 3 2 1 32 31 30
8 CY7C4281 26
14 15 16 17 18 19 20
Q0 – 8
RCLK REN1 REN2
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-06007 Rev. *B
Revised August 19, 2003
Signal Name Description
D0 – 8
Q0 − 8
Write Enable 1
Write Enable 2
Dual Mode Pin
EF Empty Flag
FF Full Flag
OE Output Enable
I Data Inputs for 9-bit bus.
O Data Outputs for 9-bit bus.
I The only write enable when device is configured to have programmable flags.
Data is written on a LOW-to-HIGH transition of WCLK when WEN1 is asserted and FF
is HIGH. If the FIFO is configured to have two write enables, data is written on a
LOW-to-HIGH transition of WCLK when WEN1 is LOW and WEN2/LD and FF are HIGH.
I If HIGH at reset, this pin operates as a second write enable. If LOW at reset, this
pin operates as a control to write or read the programmable flag offsets. WEN1 must be
LOW and WEN2 must be HIGH to write data into the FIFO. Data will not be written into
the FIFO if the FF is LOW. If the FIFO is configured to have programmable flags,
WEN2/LD is held LOW to write or read the programmable flag offsets.
I Enables the device for Read operation. Both REN1 and REN2 must be asserted to
allow a read operation.
I The rising edge clocks data into the FIFO when WEN1 is LOW and WEN2/LD is
HIGH and the FIFO is not Full. When LD is asserted, WCLK writes data into the
programmable flag-offset register.
I The rising edge clocks data out of the FIFO when REN1 and REN2 are LOW and
the FIFO is not Empty. When WEN2/LD is LOW, RCLK reads data out of the program-
mable flag-offset register.
O When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
O When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
O When PAE is LOW, the FIFO is almost empty based on the almost empty offset
value programmed into the FIFO. PAE is synchronized to RCLK.
O When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is synchronized to WCLK.
I Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
I When OE is LOW, the FIFO’s data outputs drive the bus to which they are
connected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
64k x 9
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current (ICC1)
128k x 9
Document #: 38-06007 Rev. *B
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