3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO
CY7C43642AV CY7C43662AV CY7C43682AV
3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO
Features
• 3.3V high-speed, lo...
Description
CY7C43642AV CY7C43662AV CY7C43682AV
3.3V 1K/4K/16K x36 x2 Bidirectional Synchronous FIFO
Features
3.3V high-speed, low-power, bidirectional, First-In First-Out (FIFO) memories 1K ×36 ×2 (CY7C43642AV) 4K x36 x2 (CY7C43662AV) 16K x36 x2 (CY7C43682AV) 0.25-micron CMOS for optimum speed/power High-speed 133-MHz operation (7.5-ns Read/Write cycle times) Low power — ICC = 60 mA — ISB = 10 mA Fully asynchronous and simultaneous Read and Write operations permitted Mailbox bypass register for each FIFO Parallel Programmable Almost Full and Almost Empty flags Retransmit function Standard or FWFT user-selectable mode 120-pin TQFP package Easily expandable in width and depth
Logic Block Diagram
MBF1 CLKA CSA W/RA ENA MBA RT2
Port A Control Logic Input Register
Mail1 Register 1K/4K/16K × 36 Dual Ported Memory (FIFO1)
CLKB CSB W/RB ENB MBB RT1
Register
MRST1
FIFO1, Mail1 Reset Logic
Write Pointer
Read Pointer
FFA/IRA AFA
Status Flag Logic
Output
Port B Control Logic
EFB/ORB AEB
FS0 FS1 A0–35 EFA/ORA AEA
Programmable Flag Offset Registers
Timing Mode
B0–35 FWFT/STAN
Status Flag Logic Write Pointer Read Pointer
FFB/IRB AFB
1K/4K/16K × 36 Dual Ported Memory (FIFo2) Mail2 Register
MBF2
Cypress Semiconductor Corporation Document #: 38-06020 Rev. *C
Output Register
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Input Register
FIFO2, Mail2 Reset Logic
MRST2
CA 95134 408-943-2600 Revised December 26, 2002
CY7C43642AV CY7C43662AV CY7C43682AV
P...
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