CYM1831

31 CYM1831 64K x 32 Static RAM Module Features High-density 2-Mbit SRAM module 32-bit standard footprint supports densities from 16K x 32 through 1M x 32 High-speed CMOS SRAMs — Access time of 15 ns Low active power — 5.3W (max.) SMD technology TTL-compatible inputs and outputs Low profile — Max. height of 0.50 in. Small PCB footprint — 1.2 sq. in. on an epoxy laminate board with pins. Four chip selects (CS1, CS2, CS3, and CS4) are used to independently enable the four bytes. Reading or writing can be executed on individual bytes or any combination of multiple bytes through proper use of selects. Writing to each byte is accomplished when the appropriate Chip Selects (CSN) and Write Enable (WE) inputs are both LOW. Data on the input/output pins (I/OX) is written into the memory location specified on the address pins (A0 through A15). Reading the device is accomplished by taking the Chip Selects (CSN) LOW and Output Enable (OE) LOW while Write Enable (WE) remains HIGH. Under these conditions the contents of the memory location specified on the address pins will appear on the data input/output pins (I/OX). The data input/output pins stay in the high-impedance state when Write Enable (WE) is LOW or the appropriate chip selects are HIGH. Two pins (PD0 and PD1) are used to identify module memory density in applications where alternate versions of the JEDEC-standard modules can be interchanged. Functional Description The CYM1831 is a high-performance 2-Mbit static...