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CY7B9911 Dataheets PDF



Part Number CY7B9911
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB
Datasheet CY7B9911 DatasheetCY7B9911 Datasheet (PDF)

CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage Programmable Skew Clock Buffer (LV-PSCB) Features • All output pair skew <100 ps typical (250 max.) • 3.75- to 110-MHz output operation • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted — Operation at 1⁄2 and 1⁄4 input frequency — Operation at 2x and 4x input frequency (input as low as 3.75 MHz) Zero input-to-output delay 50% duty-cycle outputs LVTTL outputs drive 50Ω terminated lines Operates from a single.

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CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage Programmable Skew Clock Buffer (LV-PSCB) Features • All output pair skew <100 ps typical (250 max.) • 3.75- to 110-MHz output operation • User-selectable output functions — Selectable skew to 18 ns — Inverted and non-inverted — Operation at 1⁄2 and 1⁄4 input frequency — Operation at 2x and 4x input frequency (input as low as 3.75 MHz) Zero input-to-output delay 50% duty-cycle outputs LVTTL outputs drive 50Ω terminated lines Operates from a single 3.3V supply Low operating current 32-pin PLCC package Jitter < 200 ps peak-to-peak (< 25 ps RMS) selectable control over system clock functions. These multipleoutput clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews and full-swing logic levels (LVTTL). Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ±6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability of the LVPSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units. Divide-by-two and divide-by-four output functions are provided for additional flexibility in designing complex clock systems. When combined with the internal PLL, these divide functions allow distribution of a low-frequency clock that can be multiplied by two or four at the clock destination. This facility minimizes clock distribution difficulty while allowing maximum system clock speed and flexibility. • • • • • • • Functional Description The CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage Programmable Skew Clock Buffer (LVPSCB) offers user- Logic Block Diagram TEST Pin Configuration PLCC 3F0 2F1 FS FILTER REF FS 4F0 4F1 4 3F1 4Q0 SELECT INPUTS (THREE LEVEL) 4Q1 VCCQ SKEW 3Q0 3Q1 SELECT 2Q0 MATRIX 2Q1 1Q0 1Q1 7B9911V–1 3 2 1 5 6 7 8 9 10 11 12 32 31 30 29 28 27 26 TEST VCCQ GND REF FB PHASE FREQ DET VCO AND TIME UNIT GENERATOR 2F0 GND 1F1 1F0 VCCN 1Q0 1Q1 GND GND 4F0 4F1 3F0 3F1 VCCN 4Q1 4Q0 GND GND CY7B9911V 25 24 23 22 2F0 2F1 13 21 14 15 16 17 18 19 20 3Q1 3Q0 FB 2Q1 2Q0 CCN CCN 1F0 1F1 V V 7B9911V–2 Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 December 1, 1999 CY7B9911V 3.3V RoboClock+ Pin Definitions Signal Name REF FB FS 1F0, 1F1 2F0, 2F1 3F0, 3F1 4F0, 4F1 TEST 1Q0, 1Q1 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1 VCCN VCCQ GND I/O I I I I I I I I O O O O PWR PWR PWR Description Reference frequency input. This input supplies the frequency and timing against which all functional variation is measured. PLL feedback input (typically connected to one of the eight outputs). Three-level frequency range select. See Table 1. Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2. Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2. Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2. Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2. Three-level select. See test mode section under the block diagram descriptions. Output pair 1. See Table 2. Output pair 2. See Table 2. Output pair 3. See Table 2. Output pair 4. See Table 2. Power supply for output drivers. Power supply for internal circuitry. Ground. Skew Select Matrix The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers (xQ0, xQ1), and two corresponding three-level function select (xF0, xF1) inputs. Table 2 below shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected. Table 2. Programmable Skew Configurations[1] Function Selects 1F1, 2F1, 3F1, 4F1 LOW LOW LOW MID MID Approximate Frequency (MHz) At Which tU = 1.0 ns 22.7 38.5 62.5 MID HIGH HIGH HIGH 1F0, 2F0, 3F0, 4F0 LOW MID HIGH LOW MID HIGH LOW MID HIGH Output Functions 1Q0, 1Q1, 2Q0, 2Q1 – 4tU – 3tU – 2tU – 1tU 0tU +1tU +2tU +3tU +4tU 3Q0, 3Q1 – 6tU – 4tU – 2tU 0tU +2tU +4tU +6tU Divide by 4 4Q0, 4Q1 – 6tU – 4tU – 2tU 0tU +2tU +4tU +6tU Inverted Block Diagram Description Phase Frequency Detector and Filter These two blocks accept inputs from the Reference Frequency (REF) input and the Feedback (FB) input and generate correction information to control the frequency of the VoltageControlled Oscillator (VCO). These blocks, along with the VCO, form a Phase-Locked Loop (PLL) that track.


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