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CY7C1041CV33 Dataheets PDF



Part Number CY7C1041CV33
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description 256K x 16 Static RAM
Datasheet CY7C1041CV33 DatasheetCY7C1041CV33 Datasheet (PDF)

CY7C1041CV33 256K x 16 Static RAM Features • Pin equivalent to CY7C1041BV33 • High speed — tAA = 10 ns • Low active power — 324 mW (max.) • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8–I/O15) is written into the location specified on the address pins (A0–A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable.

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CY7C1041CV33 256K x 16 Static RAM Features • Pin equivalent to CY7C1041BV33 • High speed — tAA = 10 ns • Low active power — 324 mW (max.) • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features HIGH Enable (BHE) is LOW, then data from I/O pins (I/O8–I/O15) is written into the location specified on the address pins (A0–A17). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is LOW, then data from memory will appear on I/O8 to I/O15. See the truth table at the back of this data sheet for a complete description of Read and Write modes. The input/output pins (I/O0–I/O15) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a Write operation (CE LOW, and WE LOW). The CY7C1041CV33 is available in a standard 44-pin 400-mil-wide body width SOJ and 44-pin TSOP II package with center power and ground (revolutionary) pinout, as well as a 48-ball fine-pitch ball grid array (FBGA) package. Functional Description[1] The CY7C1041CV33 is a high-performance CMOS Static RAM organized as 262,144 words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable (BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written into the location specified on the address pins (A0–A17). If Byte Logic Block Diagram INPUT BUFFER Pin Configuration SOJ TSOP II Top View A0 A1 A2 A3 A4 CE I/O0 I/O1 I/O2 I/O3 VCC VSS I/O4 I/O5 I/O6 I/O7 WE A5 A6 A7 A8 A9 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A0 A1 A2 A3 A4 A5 A6 A7 A8 256K × 16 ARRAY 1024 x 4096 I/O0–I/O7 I/O8–I/O15 COLUMN DECODER BHE WE CE OE BLE A17 A16 A15 OE BHE BLE I/O15 I/O14 I/O13 I/O12 VSS VCC I/O11 I/O10 I/O9 I/O8 NC A14 A13 A12 A11 A10 ROW DECODER Selection Guide -8 Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current Commercial Industrial Commercial/ Industrial 8 100 110 10 -10 10 90 100 10 -12 12 85 95 10 -15 15 80 90 10 -20 20 75 85 10 Unit ns mA mA mA Shaded areas contain advance information. Note: 1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com. Cypress Semiconductor Corporation Document #: 38-05134 Rev. *D A9 A10 A 11 A 12 A 13 A14 A15 A16 A17 SENSE AMPS • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 Revised October 18, 2002 CY7C1041CV33 Pin Configurations 48-ball Mini FBGA 1 BLE I/O0 I/O1 VSS VCC I/O6 I/O7 NC 2 OE BHE I/O 2 I/O3 I/O4 I/O5 NC A8 (Top View) 4 .


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