CY7C1380BV25

1CY7C1380BV25 PRELIMINARY CY7C1380BV25 CY7C1382BV25 512K x 36 / 1 Mb x 18 Pipelined SRAM Features Fast clock speed: 200,166, 150, 133 MHz Provide high-performance 3-1-1-1 access rate Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns Optimal for depth expansion 2.5V (±5%) Operation Common data inputs and data outputs Byte Write Enable and Global Write control Chip enable for address pipeline Address, data, and control registers Internally self-timed WRITE CYCLE Burst control pins (interleaved or linear burst sequence) Automatic power-down for portable applications High-density, high-speed packages JTAG boundary scan for BGA packaging version (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE), burst control in, and ADV), Write Enables (BWa, BWb, puts (ADSC, ADSP BWc, BWd and BWE), and global write (GW). Asynchronous inputs include the output enable (OE) and Burst Mode Control (MODE). The data (DQa,b,c,d) and the data parity (DQPa,b,c,d) outputs, enabled by OE, are also asynchronous. DQa,b,c,d and DQPa,b,c,d apply to CY7C1380BV25 and DQa,b and DQPa,b apply to CY7C1382BV25. a, b, c, d each are of 8 bits wide in the case of DQ and 1 bit wide in the case of DP . Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller (ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance Pin (ADV). Addres...