Document
CXA1784AS
US Audio Multiplexing Decoder For the availability of this product, please contact the sales office.
Description The CXA1784AS is an IC designed as a decoder for the Zenith TV Multi-channel System and also corresponds with I2C BUS. Functions include stereo demodulation, SAP (Separate Audio Program) demodulation, dbx noise reduction and sound processor. Various kinds of filters are built in while adjustment, mode control and sound processor control are all executed through I2C BUS. Features • Audio multiplexing decoder, dbx noise reduction decoder and sound processor are all included in a single chip. Almost any sort of signal processing is possible through this IC. • All adjustments are possible through I2C BUS to allow for automatic adjustment. • Various built-in filter circuits greatly reduce external parts. • There are two systems for both inputs and outputs, and each mode control is possible. Standard I/O Level • Input level COMPIN (Pin 17) AUXIN-L/R (Pins 38 and 37) • Output level TVOUT-L/R (Pins 35 and 34) LSOUT-L/R (Pins 6 and 5) Pin Configuration (Top View)
TVOUT-R SURRTC AUXIN-R VCAWGT BASSL1 VCATC VEOUT VCAIN VEWGT SAPOUT BASSR1 VETC SAPIN NOISETC BASSR2 AUXIN-L TVOUT-L
42 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta=25°C) 11 • Supply voltage VCC • Operating temperature Topr –20 to +75 • Storage temperature Tstg –65 to +150 • Allowable power dissipation PD 2.2 Range of Operating Supply Voltage 9±0.5
V °C °C W
V
Applications TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC
245 mVrms 490 mVrms 490 mVrms 490 mVrms
ITIME
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
VE
26
25
24
23
GND
20
NC
22
1
BASSL2
2
TRER
3
TREL
4
SURROUT
5
LSOUT-R
6
LSOUT-L
7
SDA
8
SCL
9
DGND
10
11
12
13
14
15
16
17
18
19
21
PLINT
SUBOUT
IREF
STFIL
MAININ
COMPIN
STIN
SAD
MAINOUT
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
SAPTC
VGR
VCC
E95430A5Z-PK
Block Diagram
MAINOUT 14
AUXIN-R 37
SUBOUT 19
AUXIN-L 38
MAININ 13
PLINT 15
STFIL 16
STLPF 35 TVOUT-L SW1 MATRIX FLT SW2 LPF VCA 34 TVOUT-R
"STLPF" 1/4 1/2
LFLT
VCO
"STEREO" WIDEBAND DeEm (+6dB) LPF NRSW/FOMO/ SAPC EXT1/EXT2/M1/M2
COMPIN
17
VCA
LPF
PREVOL 39 SURRTC SURROUND 42 BASSL1
PREVOL SURR
STIND SAPVDET "SAPVCO" LOGIC
VCC 21
INSW1 & INSW2
1
BASSL2 40 BASSR1
BASS BASS BASS
–2–
LPF DeEm "NOISE" "SAP" HPF RMSDET VE SPECTRAL LPF LPF "SAPLPF" AMP (+4dB) SW "PONRES"
GND
23
BPF
SAPVCO
41 BASSR2 VCA
NOISETC
22
NOISE DET
3
TREB TREB TREBLE
TREL
2
TRER
SAPTC 18
SAPIND MATRIX RMSDET
VOL-R
STLPF STVCO SAPLPF SAPVCO
SAPFDET
VOL-R
SURR-VOL
VOL-L
VOL-S
ITIME 33
IREF
I2 C BUS I/F
VOL-L
(L-R)
9
8
7
6
5
4
11 SDA STIN SAPIN SAPOUT
12
10
24
25
20
26 VE
27
28
29
30
31
32
SAD
SCL
SURROUT
IREF
VCAIN
DGND
LSOUT-L
LSOUT-R
VGR
VETC
VCATC
VEOUT
VEWGT
VCAWGT
CXA1784AS
CXA1784AS
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
VCC 3k
(Ta = 25 °C, VCC = 9 V) Description BASS filter pin. (Left channel) (Connect a 15 nF capacitor between Pins 1 and 42.) The cutoff frequency is determined by the built-in resistor and the external capacitance. BASS filter pin. (Right channel) (Connect a 15 nF capacitor between Pins 41 and 40.) The cutoff frequency is determined by the built-in resistor and the external capacitance.
1
BASSL2
4.0
1
41 13.2k 10.7k 8.57k 6.89k 500 500
42
BASSL1
4.0
41
BASSR2
4.0
5.66k 4.44k 3.67k
VCC
40 42
40
BASSR1
4.0
4V
15.3k
VCC 3k
2
TRER
4.0
4.2k 3.42k 2.73k 2.2k 1.8k 1.42k
500 500
TREBLE filter pin. (Right channel) (Connect a 6.8 nF capacitor between this pin and GND.)
3
TREL
4.0
VCC
1.17k 4.88k
2 3
TREBLE filter pin. (Left channel) (Connect a 6.8 nF capacitor between this pin and GND.)
VCC
4
SURROUT
4.0
VCC 500
(L - R) signal output pin.
5
LSOUT-R
4.0
4 5 6
500
LSOUT right channel output pin.
6
LSOUT-L
4.0
LSOUT left channel output pin. –3–
CXA1784AS
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC 7.5k ↓ 35µ 2.1V 4k
Description
7
SDA
—
7.5k
×2 4.5k ×5 3k
Serial data I/O pin. VIH > 3.0 V VIL < 1.5 V
7
VCC 7.5k ↓ 35µ 2.1V 4k
8
SCL
—
19.5k
×4
Serial clock input pin. VIH > 3.0 V VIL < 1.5 V
3k
8
9
DGND
—
VCC
9
Digital block GND.
2V 40k 80k
10
10
SAD
—
10k
Slave address control switch. The slave address is selected by changing the voltage applied to this pin.
3k
147
11
VGR
1.3V
11k
9.7k
19.4k ×4
VCC 11k 11k
Band gap reference output pin. (Connect a 10 µF capacitor between this pin and GND.)
11 2.06k
–4–
CXA1784AS
Pin No.
Sy.