Document
CXA2050S
Y/C/RGB/D for PAL/NTSC Color TVs
Description The CXA2050S is a bipolar IC which integrates the luminance signal processing, chroma signal processing, RGB signal processing, and sync and deflection signal processing functions for PAL/NTSC system color TVs onto a single chip. This IC includes deflection processing functions for wide-screen TVs, and is also equipped with a SECAM decoder interface, making it possible to construct a TV system that supports multiple color systems. 64 pin SDIP (Plastic)
Features • I2C bus compatible • Compatible with both PAL and NTSC systems (also compatible with SECAM if a SECAM decoder is connected) • Built-in deflection compensation circuit capable of supporting various wide modes • Countdown system eliminates need for H and V oscillator frequency adjustment • Automatic identification of 50/60Hz vertical frequency (forced control possible) • Non-interlace display support (even/odd selectable) • Automatic identification of PAL, NTSC, and SECAM color systems (forced control possible) • Automatic identification of 4.43MHz/3.58MHz crystal (forced control possible) • Non-adjusting Y/C block filter • One CV input, one set of Y/C inputs, two sets of analog RGB inputs (one set of which can serve as both analog and digital inputs) • Built-in AKB circuit • Support for forcing YS1 off Applications Color TVs (4:3, 16:9) Structure Bipolar silicon monolithic IC Absolute Maximum Ratings (Ta = 25°C, SGND, DGND = 0V) • Supply voltage SVCC1, 2, DVCC1, 2 –0.3 to +12 V • Operating temperature Topr –20 to +65 °C • Storage temperature Tstg –65 to +150 °C • Allowable power consumption PD 1.7 W • Voltages at each pin –0.3 to SVCC1, SVCC2, DVCC1, DVCC2 + 0.3 V Operating Conditions Supply voltage
SVCC1, 2 DVCC1, 2
9.0 ± 0.5 9.0 ± 0.5
V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96403-PS
Block Diagram
EXT SYNC IN
VM
SYNCOUT
SDA
DCTRAN
SCL
BLHOLD
VSFIL
HSIN
CERA
VSIN
63
54 59 52 47 44
57 61
56
55 51 45
53 46
2Vp-p H SYNC SEP 32fH VCO PHASE DET V SYNC SEP GATE Sand Castle PHASE DET. 1/32 2fH H POSI AFC CD MODE PHASE SHIFT DC SHARP TRAN AGING D PIC DL SHP f0 V FREQ 50/60 ID SHARP NESS D PIC GATE Count Down 525/625 PRE/OVER TOT TOT INTERLACE PIC D-COL γ KILLER DET YS1 OFF INTER -LACE
AFCFIL
AFCPIN/ HOFF
L2FIL
42 DVCC1 50 DVCC2 48 DGND H.DRIVE 43 HD OUT 12 SCPOUT 36 VTIM 40 VAGCSH VPOSI, VOFF, VSIZE
6dB
VM
EXT SYNC
VIDEO OUT 58
CV/YC
SUB CONT DL DC TRAN CLP
TRAP OFF
CVIN 60
1Vp-p
YIN 62
VIDEO SW
SUB CONT
TRAP
ACC DET
SYSTEM IDENT
1Vp-p
YS2
YM
RSH
B1IN
IREF
R2IN
X358
X443
R1IN
G1IN
YOUT
YRET
G2IN
B2IN
APCFIL
ABLFIL
FSCOUT
SECAM REF.