Document
CXD1198AQ
CD-ROM Subcode Decoder For the availability of this product, please contact the sales office.
Description The CXD1198AQ is a CD-ROM subcode decoder LSI. Features • Real time error correction of subcodes • Connection possible with DRAM up to 1 MB as buffer memory • Automatic generation of sync patterns • Error pointer buffering function (separated mode, mixed mode) • 4 MB/s maximum rate for transferring data with SCSI control LSI Applications CD-ROM drives Structure Silicon gate CMOS IC 100 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC –0.5 to +7.0 V • Input voltage VI –0.5 to VDD +0.5 V • Output voltage VO –0.5 to VDD +0.5 V • Operating temperature Topr –20 to +75 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD 5.0±0.5 • Operating temperature Topr –20 to +75
V °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E92632A78-TE
CXD1198AQ
Block Diagram
30 DMA Refresh Control 81 88 DDBP 80 XDAC 75 DDRQ 76 XDWR 89 XDRD 91 XDCA 92 93 DA0,1 94 XDRS 77 I n t e r f a c e C o n t r o l
27
26
31-39,41
18-25
DMA Controller (priority resolver, sequencer) H O S T Pointer DMA Control HOST DMA Control I n t e r f a c e C o n t r o l
BDB0-7
BA0-9
XRAS
XCAS
XWE
52 HMDS 71 HINT 72 HINP 55 62 67 XHAC/ SDRQ 66 HDRQ/ XSAC 64 XHWR 63 XHRD 68 XHCS 69 HA0,1 70 50 XSRS 51 XHRS
DDB0-7
D r i v e
Drive DMA Control Pointer S/P
HBD0-7
Sync. Pattern
FIFO (10bytes x 2)
Error Corrector WFCK 45 SCOR 44 SBSO 43 EXCK 42 De-Interleave CPU Interface, DMA Control Reset Control Subcode Interface S/P Control Subcode DMA Control
RAM
48 HCLK 1/2 Internal Clock 46 47 XTL2 XTL1
16 INTP
17 INT
13 XCS
11 XRD
12 XWR
95-100 A0-5
1,2,5-10 DB0-7
14 XCRS
49 XRST
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CXD1198AQ
Pin Description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Symbol DB0 DB1 VDD VSS DB2 DB3 DB4 DB5 DB6 DB7 XRD XWR XCS XCRS VSS INTP INT BDB0 BDB1 BDB2 BDB3 BDB4 BDB5 BDB6 BDB7 XWE XCAS VDD VSS XRAS BA0 BA1 BA2 BA3 I/O I/O I/O Description CPU data bus CPU data bus Power supply (+5 V) GND CPU data bus CPU data bus CPU data bus CPU data bus CPU data bus CPU data bus Register read strobe negative logic signal in this IC Register write strobe negative logic signal in this IC Chip select signal to this IC Reset negative logic signal to CPU GND INT signal polarity control input signal Interrupt request signal to CPU Buffer memory data bus Buffer memory data bus Buffer memory data bus Buffer memory data bus Buffer memory data bus Buffer memory data bus Buffer memory data bus Buffer memory data bus Strobe negative logic signal for writing in buffer memory Strobe negative logic signal for column address in buffer memory Power supply (+5 V) GND Strobe negative logic signal for row address in buffer memory Buffer memory address Buffer memory address Buffer memory address Buffer memory address
I/O I/O I/O I/O I/O I/O I I I O I O I/O I/O I/O I/O I/O I/O I/O I/O O O
O O O O O
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CXD1198AQ
Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
Symbol BA4 BA5 BA6 BA7 BA8 VSS BA9 EXCK SBSI SBSY WFCK XTL2 XTL1 HCLK XRST XSRS XHRS HMDS VDD VSS HDB7 HDB6 HDB5 HDB4 HDB3 HDB2 HDB1 HDB0 XHRD XHWR VSS HDRQ /XSAC XHAC /SDRQ
I/O O O O O O O O I I I O I O I I O I
Description Buffer memory address Buffer memory address Buffer memory address Buffer memory address Buffer memory address GND Buffer memory address Subcode data readout clock output signal to the CXD2500 Subcode data input signal from the CXD2500 Subcode frame sync input signal from the CXD2500 Write frame clock input signal from the CXD2500 Crystal oscillator circuit output Crystal oscillator circuit input Crystal 1/2 frequency-divided clock output Reset negative logic input signal SCSI bus reset negative logic input signal Reset negative logic output signal to host Host mode select input signal Power supply (+5 V) GND Host data bus Host data bus Host data bus Host data bus Host data bus Host data bus Host data bus Host data bus Data read strobe signal from host or to SCSI control IC Data write strobe signal from host or to SCSI control IC GND Data request positive logic signal to host or DMA acknowledge negative logic signal to SCSI control IC DMA acknowledge negative logic signal from host or data request positive logic signal from SCSI control IC
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
O I
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CXD1198AQ
Pin No. 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Symbol XHCS HA0 HA1 HINT HINP NC1 NC2 XDAC DDRQ XDRS VDD VS.