Document
CXD2027Q/R
DBS Audio Signal Processor For the availability of this product, please contact the sales office.
Description The CXD2027Q/R are audio signal processors designed for DBS applications. These LSIs perform all digital processing from QPSK demodulation to analog audio output on a single chip. Features QPSK and PCM demodulators and DAC output are configured on a single chip. Descrambler interface according to the COATEC system and SkyPort system . Functions QPSK demodulator • Carrier, clock and data regeneration • ALC and VCXO adjustment-free PCM demodulator • Frame sync protection by correlation detection • De-interleaving and descrambling • BCH error correction, range bit error correction • Audio data range control Expansion from 10 to 14 bits in A mode Upper bit majority correction in B mode • Control sign integration correction, chargeable flag integration correction by master frame synchronization • Interface output for external DAC • Digital interface output 1-bit DAC output • Quadruple oversampling filter • Digital de-emphasis circuit • 1-bit stereo DAC with 2nd-order ∆∑ format noise shaper S/N ratio : 90dB (Typ.) Distortion : 0.011% (Typ.) CPU interface • I2C bus Descrambler interface • COATEC system, SkyPort system Mute functions • Error occurrence frequency detection mute • Audio chargeable flag detection mute • Control sign (B7) detection mute Structure Silicon gate CMOS IC Applications TVs, VCRs with built-in BS tuners Absolute Maximum Ratings (Ta = 25°C, Vss = 0V) • Supply voltage VDD Vss – 0.5 to +7.0 V • Input voltage VI Vss – 0.5 to VDD + 0.5 V • Output voltage VO Vss – 0.5 to VDD + 0.5 V • Storage temperature Tstg –55 to +150 °C Operating Conditions • Supply voltage VDD • Operating temperature Topr CXD2027Q 64 pin QFP (Plastic) CXD2027R 80 pin LQFP (Plastic)
4.75 to 5.25 –20 to +75
V °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E94808-ST
Block Diagram
DATB DATO DSLB DSLA BITI DATA NSYN
13 9 8
BITO
6 5 7 48
4
RT FRAME SYNC DE-SCRAMBLER BCH DECODER (63, 56) SHIFTER & RANGE BIT BCH (7, 3)
71
ADIN
73
ADC
DATA RECOVERY
RB 76
GR 77
MASTER FRAME SYNC
DE-INTERLEAVER 4 kBIT-RAM
10 → 14 BIT DATA EXPAND
MAJORITY ERROR CORRECTION
MUTE SIGNAL GENERATOR
54 MUTE
ALCO
67
ALC SIGNAL GENERATOR
CONTROL WORD INTEGRAL CORRECTION
8TH RANGE BIT INTEGRAL CORRECTION
–2–
AUDIO DATA INTERPOLATOR TIMING GENERATOR I2C BUS I/F DIGITAL INTERFACE 11 14 47 50 51 38 15
CLOCK GENERATOR 28 LPO
PHAA
66 DAC1 DIGITAL FILTER DE-ENPHASIS DAC2 32 RPO 25 LNO
CARRIER RECOVERY
M23I
65
SYSTEM CLOCK GENERATOR
35
M23O
64
RNO
43 AUD 44 AUDIO INTERFACE 45 BCLK 46 F256 LRCK
PHAB
58
CLOCK .