Document
CXD2315Q
10-bit 80MSPS 1ch D/A Converter (Ultra-low Glitch Version)
Description The CXD2315Q is a 1-ch 10-bit 80MSPS D/A converter for monitor and video. This IC achieves high specifications for the industrial and information equipment due to the reduction of the glitch energy. Features • 10-bit resolution • Maximum conversion rate 80MSPS • Differential linearity error ±0.5LSB • Low power consumption 150 mW (Max., When 80MSPS 200 Ω load, 2 Vp-p is output) • Pin-compatible with CXD2306Q • Single 5 V power supply • Built-in independent constant-voltage source • Ultra-low glitch • Stand-by function Structure Silicon gate CMOS IC 32 pin QFP (Plastic)
Absolute Maximum Ratings (Ta=25 °C) • Supply voltage AVDD, DVDD 7 V • Input voltage (All pins) VIN VDD +0.5 to VSS –0.5 V • Output voltage (for each channel) IOUT 0 to 15 mA • Storage temperature Tstg –55 to +150 °C
Recommended Operating Conditions • Supply voltage AVDD, AVSS 5.0 ± 0.25 DVDD, DVSS 5.0 ± 0.25 • Reference input voltage VREF 0.5 to 2.0 • Clock pulse width tpw1, tpw0 5.6 (min.) • Operating temperature Topr –20 to +85
V V V ns °C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E95704D01
CXD2315Q
Block Diagram
(LSB) D0 30 D1 31 D2 32 D3 D4 D5 D7 (MSB) D9 1 2 3 5 DECODER 19 VREF CURRENT CELLS (FOR FULL SCALE) CLOCK GENERATOR 17 IREF 21 AVDD BAND GAP REFERENCE 20 AVDD 18 SREF 7 DECODER 6MSB'S CURRENT CELLS LATCHES 23 IO 22 VG 4LSB'S CURRENT CELLS 24 IO 25 AVSS
D6 4 D8 6 DVDD 28 BLK 10 DVDD 13 DVSS 15 DVSS 27 CLK 9 VB 14 CE 11
BIAS VOLTAGE GENERATOR
Pin Configuration
VREF AVDD SREF
18
AVDD
VG
IO
IO
24
23
22
21
20
19
17
AVss 25 NC 26 DVss 27 DVDD 28 NC 29 D0 (LSB) 30 D1 31 D2 32
IREF
16 NC 15 DVss 14 VB 13 DVDD 12 NC 11 CE 10 BLK 9 CLK
1
2
3
4
5
6
7
8
D5
27 17
to 15 to 25
Digital section Analog section
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D9 (MSB)
NC
D4
D3
D6
D7
D8
CXD2315Q
Pin Description and Equivalent Circuit Pin No. Symbol I/O Equivalent circuit
DVDD
Description
30 to 32 1 to 7
30
D0 to D9
I
to 7 DVSS
Digital input. 30 pin D0 (LSB) to 7 pin D9 (MSB)
8, 12, 16, 26, 29 9
NC CLK
—
10
BLK
I
9 10 11
DVDD
DVSS
11
CE
13, 28
DVDD
—
DVDD
No connection. Clock input. Blanking input. This is synchronized with the clock input signal. No signal (0 V output) at high and output state at low. Chip enable input. This is not synchronized with the clock input signal. No signal (0 V output) at high makes power consumption minimum. Digital power supply.
DVDD
14
VB
O
14
Connect a capacitor of approximately 0.1 µF.
DVSS
15, 27
DVSS
—
AVDD AVDD
Digital ground. Reference current output. Connect resistance “RIR” which is 16 times output resistance “ROUT”. Reference voltage input. Sets output full scale value. Connect a capacitor of approximately 0.1 µF.
17
IREF
O
AVDD 17 AVss 19 AVSS 22 AVSS AVDD
19
VREF
I
22
VG
O
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CXD2315Q
Pin No.
Symbol
I/O
Equivalent circuit
AVDD
Description Independent constant-voltage source output pin using band gap reference. Stable voltage independent of the fluctuation for supply voltage can be get by connecting to VREF. See Application Circuit 2 for details.
18
18
SREF
O
AVSS
AVSS
20, 21
AVDD
—
Analog VDD
23
IO
24 AVSS
Inverted current output. Connect to GND normally.
O
23
24
IO
AVSS
Current output. Output can be retrieved by connecting resistance. The standard is 200 Ω. Analog ground.
25
AVSS
—
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CXD2315Q
Electrical Characteristics Item Resolution Conversion speed Integral non-linearity error Differential non-linearity error Precision guaranteed output voltage range Output full-scale voltage Output full-scale current Output offset voltage Glitch energy Differential gain Differential phase Supply current Analog input resistance Input capacitance Digital input voltage Digital input current SREF output voltage Setup time Hold time Rise time Propagation delay time CE enable time ∗ CE disable time ∗
(FCLK=80 MHz, AVDD=DVDD=5 V, ROUT=200 Ω, RIR=3.3 kΩ, VREF=2.0 V, Ta=25 °C) Symbol n FCLK EL ED VOC VFS IFS VOS GE DG DP IDD ISTB RIN CI VIH VIL IIH IIL VSR ts th tr tPD tE tD Measurement conditions AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +85 °C Endpoint Min. Typ. 10 Max. Unit bit MSPS LSB LSB V V mA mV pV•s % deg mA MΩ pF V µA V ns ns ns ns ms ms
0 –1.5 –0.5 1.8 1.8 9.0 1.94 1.94 9.7
80 1.5 0.5 2.0 2.0 10 1 30 1.0 1.0 30 1 9
When D0 to D9= “0000000000” input
CE= “L” CE= “H” VREF AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C AVDD=DVDD=4.75 to 5.25 V Ta=–20 to +75 °C
1 2.45 0.85 –5 1.0 3.0 3.0 5 1.2 5 1.45
CE= H→L CE= L→H
5 1 1
2 2
∗ When the external capacitor for the VGR,VGG and VGB pins are 0.1 µF. Electrical Characteristics Measuremen.