Document
CXD2719Q
Single-Chip Dolby Pro Logic Surround Decoder
Description The CXD2719Q is a CMOS LSI developed for Dolby Pro Logic Surround. A SRAM for short delay and AD/DA converters are built in, and all functions necessary for Dolby Pro Logic Surround such as an adaptive matrix, a passive decoder including BNR, auto input balance, a noise sequencer and center channel mode control are contained on a single chip. Features • Dolby Pro Logic Surround decoding with a single chip • 2-channel 1-bit AD converter, decimation filter and prefilter operational amplifier • 4-channel 1-bit DA converter, oversampling filter and post filter • Analog switch for DSP bypass • Analog electronic attenuator (+1.5 to –29.5dB) for center/surround channel trim • 24K-bit SRAM for short delay • No separation or other variance for digital processing • External parts reduced by incorporating analog circuits Functions • Adaptive matrix • Center channel mode control (Normal/Phantom/Wide) • Dolby 3 Stereo • Auto input balance control (ON/OFF) • Noise sequencer • Variable delay time (0 to 34.8ms) • 7 kHz low-pass filter (12dB/Oct) • Modified Dolby B-type NR • Simple SFC function • SFC mode • DSP bypass mode (L, R-channel through) Structure Silicon gate CMOS Applications Equipment having Dolby Pro Logic Surround function such as AV amplifiers, receivers and compact music systems 80 pin QFP (Plastic)
Absolute Maximum Ratings (Ta = 25°C, VSS = 0V) • Supply voltage VDD VSS – 0.5 to +7.0 V • Input voltage VI VSS – 0.5 to VDD + 0.5 V • Output voltage VO VSS – 0.5 to VDD + 0.5 V • Operating temperature Topr –20 to +70 °C • Storage temperature Tstg –55 to +150 °C Recommended Operating Conditions • Supply voltage VDD Analog system 4.75 to 5.25 (5.0 typ.) V Digital system 4.50 to 5.25 (5.0 typ.) V • Operating temperature Ta –20 to +70 °C Input/Output Capacitance • Input capacitance CIN 9 (max.) pF • Output capacitance COUT 11 (max.) pF • Input/output capacitance CI/O 11 (max.) pF ∗ Measurement conditions: VDD = VI = 0V, F = 1MHz Maximum Current Consumption (Ta = 25°C, VDD = 5.25V) • Digital/analog block total: 166.7mA Dolby level • During analog input: 200 to 300mVrms • During digital input: –20dBFS Analog characteristics Pro Logic ON: Dolby level = 300mVrms Prefilter gain = –3.52dB • S/N: L, Rch = 80dB, C, Sch = 72dB • THD + N: L, Rch = 0.015%, C, Sch = 0.03% ∗ All values for typ.
This device is available only to parties obtaining the license from Dolby Laboratories Licensing Corporation. "Dolby", the double-D symbol and "Pro Logic" are trademarks of Dolby Laboratories Licensing Corporation. Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
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E98944-PS
CXD2719Q
Block Diagram
24K bit DELAY RAM 27 LIN
RVDT 50 SCK 46 XLAT 49 REDY 47 DSP LRCK 58 BCK 57 SI 55 SERIAL DATA I/F MICROCOMPUTER I/F
ADC1
26 LO1 38 RIN
ADC2
39 LO2
DAC1 Analog SW DAC2 Analog SW DAC3 Trim Vol
23 LOUT
42 ROUT
30 XCOUT (Phase Inverted Output) 35 XSOUT (Phase Inverted Output)
XMST 60
CLOCK GENERATOR /TIMING CIRCUIT
DAC4
Trim Vol
33
32
17
XTLO
XTLI
Pin Configuration
XMST ROUT RVDT REDY LRCK AVS4 AVD4 VSS5 VSS4 T.P T.P AVD2
40 AVS2 39 LO2 38 RIN 37 AVD6 36 AVS6 35 XSOUT 34 AVSX 33 XTLI 32 XTLO 31 AVDX 30 XCOUT 29 AVS5 28 AVD5 27 LIN 26 LO1 25 AVS1
BFOT
VDD1
XS24
XLAT
VSS6
BCK
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
T.P 65 T.P 66 T.P 67 T.P 68 T.P 69 T.P 70 T.P 71 T.P 72 VDD2 73 VSS7 74 T.P 75 T.P 76 T.P 77 T.P 78 T.P 79 T.P 80
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCK
T.P
VSS3
T.P
T.P
T.P
SI
BFOT
XRST
LOUT
T.P
VSS1
AVS3
AVD3
T.P
VDD0
TST0
TST4
VSS0
TST3
CSL2
TST2
VSS2
T.P
T.P
T.P
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AVD1
CSL1
T.P
T.P
TST1
CXD2719Q
Pin Description Pin No. 1 to 3 4 5 to 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol T.P VSS0 T.P TST0 VDD0 VSS1 TST1 TST2 TST3 TST4 XRST BFOT CSL1 CSL2 VSS2 AVS3 AVD3 LOUT AVD1 AVS1 LO1 LIN AVD5 AVS5 XCOUT AVDX XTLO XTLI AVSX XSOUT AVS6 AVD6 I/O O — O I — — I I I I I O I I — — — O — — O I — — O — O I — O — —
Notations in parentheses indicate the fixed pin connection status. Description Test monitor. Normally outputs Low. Digital GND. Test monitor. Normally outputs Low. Test. Normally fixed Low. Digital power supply. Digital GND. Test. Normally fixed Low. Test. Normally fixed Low. Test. Normally fixed Low. Test. Normally fixed Low. System reset input. Reset when Low. Clock, frequency-division output. [384/768/256/512fs] Test. Normally fixed High. Test. Normally fixed Low. Digital GND. L-ch DA converter GND. L-ch DA converter power supply. L-ch DA converter output. .