CXL5504P

CXL5504M/P CMOS-CCD 1H Delay Line for NTSC For the availability of this product, please contact the sales office. Description The CXL5504M/P are CMOS-CCD delay line ICs that provide 1H delay time for NTSC signals including the external low-pass filter. Features Single power supply (5V) Low power consumption 90mW (Typ.) Built-in peripheral circuits Clamp level of I/O signal can be selected Functions 905-bit CCD register Clock driver Autobias circuit Input clamp circuit Sample and hold circuit Structure CMOS-CCD CXL5504M 8 pin SOP (Plastic) CXL5504P 8 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) Supply voltage VDD 6 V Operating temperature Topr –10 to +60 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD CXL5504M 350 mW CXL5504P 480 mW Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) Input clock amplitude VCLK 0.4 to 1.0 Vp-p (0.5Vp-p typ.) Clock frequency fCLK 14.318182 MHz Input clock waveform Sine wave Input Signal Amplitude VSIG 500mVp-p (Typ.), 572mVp-p (Max.) (at internal clamp condition) Blook Diagram and Pin Configration (Top View) CLK 5 Timing circuit Clock driver Bias circuit (A) Output circuit (S/H 1bit) Clamp circuit I/O control Bias circuit (B) 4 8 7 6 Autobias circuit Bias circuit CCD (905bit) 1 2 3 IN I/O2 OUT I/O1 VDD AB Sony reserves the right to change products and specifications without prior notice. This informat...