CXL5507M

CXL5507M/P CMOS-CCD 1H Delay Line for NTSC Description The CXL5507M/P are CMOS-CCD delay line ICs that provide 1H delay time for NTSC signals including the external low-pass filter. Features Single 5V power supply Low power consumption 50mW (Typ.) Built-in peripheral circuits Functions 453-bit CCD register Clock driver Auto-bias circuit Input clamp circuit Sample-and-hold circuit Structure CMOS-CCD CXL5507M 8 pin SOP (Plastic) CXL5507P 8 pin DIP (Plastic) Absolute Maximum Ratings (Ta = 25°C) 6 V Supply voltage VDD Operating temperature Topr –10 to +60 °C Storage temperature Tstg –55 to +150 °C Allowable power dissipation PD CXL5507M 350 mW CXL5507P 480 mW Recommended Operating Condition (Ta = 25°C) Supply voltage VDD 5 ± 5% V Recommended Clock Conditions (Ta = 25°C) Input clock amplitude VCLK 0.3 to 1.0 Vp-p (0.5Vp-p typ.) Clock frequency fCLK 7.159090 MHz Input clock waveform Sine wave Blook Diagram and Pin Configuration (Top View) AB VDD Input Signal Amplitude VSIG 500mVp-p (Typ.), 527mVp-p (Max.) (at internal clamp condition) VGA 6 8 7 Auto-bias circuit Bias circuit Timing circuit CCD (453bit) Clock driver Bias circuit (A) Output circuit (S/H 1bit) Bias circuit (B) Clamp circuit 1 2 3 4 VGB OUT Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are ...