CXL5512P

CXL5512M/P CMOS-CCD 1H Delay Line for NTSC Description The CXL5512M/P are CMOS-CCD delay line ICs designed for processing video signals. This ICs provide a 1H delay time for NTSC signals including the external lowpass filter. Features Single 5 V power supply Low power consumption Built-in peripheral circuit Built-in tripling PLL circuit Sync tip clamp mode Absolute Maximum Ratings (Ta=25 °C) Supply voltage VDD +6 Operating temperature Topr –10 to +60 Storage temperature Tstg –55 to +150 Allowable power dissipation PD CXL5512M 350 CXL5512P 480 Recommended Operating Range (Ta=25 ˚C) VDD 5 V±5 % Recommended Clock Conditions (Ta=25 ˚C) Input clock amplitude VCLK 400mVp-p (Typ.) Clock frequency fCLK 3.579545 MHz Input clock waveform Sine wave Block Diagram and Pin Configuration VDD VCO OUT VCO IN CLK CXL5512M 8 pin SOP (Plastic) CXL5512P 8 pin DIP (Plastic) Input Signal Amplitude VSIG 500mVp-p (typ.), 572 mVp-p (max.) (at internal clamp condition) Functions 680-bit CCD register Clock driver Auto-bias circuit Sync tip clamp circuit Sample and hold circuit Tripling PLL circuit Inverted output Structure CMOS-CCD V °C °C mW mW 8 7 6 5 PLL Auto-bias circuit Timing circuit CCD (680bit) Output circuit (S/H 1 bit) Clamp circuit Clock driver Bias circuit A Bias circuit B 1 IN 2 AB 3 OUT 4 VSS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implicati...