2SJ130L

2SJ130(L), 2SJ130(S) Silicon P-Channel MOS FET Application High speed power switching Features Low on-resistance High speed switching Low drive current No secondary breakdown Suitable for switching regulator, DC-DC converter and ultrasonic power oscillators Outline DPAK-1 4 4 1 1 D G 1. Gate 2. Drain 3. Source 4. Drain S 2 3 2 3 2SJ130(L), 2SJ130(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Channel dissipation Channel temperature Storage temperature Note: 1. Value at TC = 25°C Symbol VDSS VGSS ID I D(pulse) I DR Pch* Tch Tstg 1 Ratings –300 ±20 –1 –2 –1 20 150 –55 to +150 Unit V V A A A W °C °C Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Gate to source leak current Symbol Min V(BR)DSS V(BR)GSS I GSS –300 ±20 — — –2.0 — 0.25 — — — — — — — — — Typ — — — — — 6.0 0.4 235 65 16 10 25 35 45 –0.9 200 Max — — ±10 –100 –4.0 8.5 — — — — — — — — — — Unit V V µA µA V Ω S pF pF pF ns ns ns ns V ns I F = –1 A, VGS = 0 I F = –1 A, VGS = 0, diF/dt = 50 A/µs I D = –0.5 A, VGS = –10 V, RL = 60 Ω Test conditions I D = –10 mA, VGS = 0 I G = ±100 µA, VDS = 0 VGS = ±16 V, VDS = 0 VDS = –240 V, VGS = 0 I D = –1 mA, VDS = –10 V I D = –0.5 A, VGS = –10 V*1 I D = –0.5 A, VDS = –20 V*1 VDS = –10 V, VGS = 0, f = 1 MHz Zero gate voltage drain current I DSS Gate to source cutoff voltage Static drai...