2SJ505S

2SJ505(L), 2SJ505(S) Silicon P Channel MOS FET High Speed Power Switching ADE-208-547 Target specification 1st. Edition Features Low on-resistance R DS(on) = 0.017Ω typ. Low drive current. 4V gate drive devices. High speed switching. Outline LDPAK 4 D 1 G 1 4 2 3 2 3 1. Gate 2. Drain 3. Source 4. Drain S 2SJ505(L), 2SJ505(S) Absolute Maximum Ratings (Ta = 25°C) Item Drain to source voltage Gate to source voltage Drain current Drain peak current Body to drain diode reverse drain current Avalanche current Avalanche energy Channel dissipation Channel temperature Storage temperature Symbol VDSS VGSS ID I D(pulse)* I DR I AP * 3 3 2 1 Ratings –60 ±20 –50 –200 –50 –50 214 75 150 –55 to +150 Unit V V A A A A mJ W °C °C EAR* Pch* Tch Tstg Notes: 1. PW ≤ 10 µs, duty cycle ≤ 1 % 2. Value at Tc = 25°C 3. Value at Ta = 25°C, Rg ≥ 50 Ω, L=100µH 2 2SJ505(L), 2SJ505(S) Electrical Characteristics (Ta = 25°C) Item Drain to source breakdown voltage Gate to source breakdown voltage Zero gate voltege drain current Gate to source leak current Symbol V(BR)DSS V(BR)GSS I DSS I GSS Min –60 ±20 — — –1.0 — — 27 — — — — — — — — — Typ — — — — — 0.017 0.024 39 4100 2100 450 32 225 530 330 –1.1 110 Max — — –10 ±10 –2.0 0.022 0.036 — — — — — — — — — — Unit V V µA µA V Ω Ω S pF pF pF ns ns ns ns V ns I F = –50A, VGS = 0 I F = –50A, VGS = 0 diF/ dt = 50A/µs Test Conditions I D = –10mA, VGS = 0 I G = ±100µA, VDS = 0 VDS = –60 V, VGS = 0 VGS = ±16V, VDS = 0 I D = –1mA, VDS = –10V I D = ...