4042B D-latch Datasheet

4042B Datasheet, PDF, Equivalent


Part Number

4042B

Description

Quadruple D-latch

Manufacture

NXP

Total Page 6 Pages
Datasheet
Download 4042B Datasheet


4042B
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4042B
MSI
Quadruple D-latch
Product specification
File under Integrated Circuits, IC04
January 1995

4042B
Philips Semiconductors
Quadruple D-latch
Product specification
HEF4042B
MSI
DESCRIPTION
The HEF4042B is a 4-bit latch with four data inputs (D0 to
D3), four buffered latch outputs (O0 to O3), four buffered
complementary latch outputs (O0 to O3) and two common
enable inputs (E0 and E1). Information on D0 to D3 is
transferred to O0 to O3 while both E0 and E1 are in the
same state, either HIGH or LOW. O0 to O3 follow D0 to
D3 as long as both E0 and E1 remain in the same state.
When E0 and E1 are different, D0 to D3 do not affect O0 to
O3 and the information in the latch is stored.
O0 to O3 are always the complement of O0 to O3. The
exclusive-OR input structure allows the choice of either
polarity for E0 and E1. With one enable input HIGH, the
other enable input is active HIGH; with one enable input
LOW, the other enable input is active LOW.
Fig.2 Pinning diagram.
HEF4042BP(N): 16-lead DIL; plastic
(SOT38-1)
HEF4042BD(F): 16-lead DIL; ceramic (cerdip)
(SOT74)
HEF4042BT(D): 16-lead SO; plastic
(SOT109-1)
( ): Package Designator North America
PINNING
D0 to D3
E0 and E1
O0 to O3
O0 to O3
data inputs
enable inputs
parallel latch outputs
complementary parallel latch outputs
APPLICATION INFORMATION
Some examples of applications for the HEF4042B are:
Buffer storage
Holding register
FAMILY DATA, IDD LIMITS category MSI
See Family Specifications
Fig.1 Functional diagram.
January 1995
2


Features INTEGRATED CIRCUITS DATA SHEET For a co mplete data sheet, please also download : • The IC04 LOCMOS HE4000B Logic Fam ily Specifications HEF, HEC • The IC0 4 LOCMOS HE4000B Logic Package Outlines /Information HEF, HEC HEF4042B MSI Qua druple D-latch Product specification F ile under Integrated Circuits, IC04 Jan uary 1995 Philips Semiconductors Prod uct specification Quadruple D-latch D ESCRIPTION The HEF4042B is a 4-bit latc h with four data inputs (D0 to D3), fou r buffered latch outputs (O0 to O3), fo ur buffered complementary latch outputs (O0 to O3) and two common enable input s (E0 and E1). Information on D0 to D3 is transferred to O0 to O3 while both E 0 and E1 are in the same state, either HIGH or LOW. O0 to O3 follow D0 to D3 a s long as both E0 and E1 remain in the same state. When E0 and E1 are differen t, D0 to D3 do not affect O0 to O3 and the information in the latch is stored. O0 to O3 are always the complement of O0 to O3. The exclusive-OR input structure allows the choice of either .
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