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4046B Dataheets PDF



Part Number 4046B
Manufacturers NXP
Logo NXP
Description Phase-locked loop
Datasheet 4046B Datasheet4046B Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4046B MSI Phase-locked loop Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Phase-locked loop DESCRIPTION The HEF4046B is a phase-locked loop circuit that consists of a linear voltage controlled oscillator (VCO) .

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4046B MSI Phase-locked loop Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Phase-locked loop DESCRIPTION The HEF4046B is a phase-locked loop circuit that consists of a linear voltage controlled oscillator (VCO) and two different phase comparators with a common signal input amplifier and a common comparator input. A 7 V regulator (zener) diode is provided for supply voltage regulation if necessary. For functional description see further on in this data. HEF4046B MSI Fig.1 Functional diagram. FAMILY DATA HEF4046BP(N): HEF4046BD(F): HEF4046BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America IDD LIMITS category MSI See further on in this data. See Family Specifications January 1995 2 Philips Semiconductors Product specification Phase-locked loop PINNING 1. Phase comparator pulse output 2. Phase comparator 1 output 3. Comparator input 4. VCO output 5. Inhibit input 6. Capacitor C1 connection A 7. Capacitor C1 connection B 8. VSS 9. VCO input 10. Source-follower output 11. Resistor R1 connection 12. Resistor R2 connection 13. Phase comparator 2 output 14. Signal input HEF4046B MSI 15. Zener diode input for regulated supply. Fig.2 Pinning diagram. FUNCTIONAL DESCRIPTION VCO part The VCO requires one external capacitor (C1) and one or two external resistors (R1 or R1 and R2). Resistor R1 and capacitor C1 determine the frequency range of the VCO. Resistor R2 enables the VCO to have a frequency off-set if required. The high input impedance of the VCO simplifies the design of low-pass filters; it permits the designer a wide choice of resistor/capacitor ranges. In order not to load the low-pass filter, a source-follower output of the VCO input voltage is provided at pin 10. If this pin (SFOUT) is used, a load resistor (RSF) should be connected from this pin to VSS; if unused, this pin should be left open. The VCO output (pin 4) can either be connected directly to the comparator input (pin 3) or via a frequency divider. A LOW level at the inhibit input (pin 5) enables the VCO and the source follower, while a HIGH level turns off both to minimize stand-by power consumption. Phase comparators The phase-comparator signal input (pin 14) can be direct-coupled, provided the signal swing is between the standard HE4000B family input logic levels. The signal must be capacitively coupled to the self-biasing amplifier at the signal input in case of smaller swings. Phase comparator 1 is an EXCLUSIVE-OR network. The signal and comparator input frequencies must have a 50% duty January 1995 3 factor to obtain the maximum lock range. The average output voltage of the phase comparator is equal to 1⁄2 VDD when there is no signal or noise at the signal input. The average voltage to the VCO input is supplied by the low-pass filter connected to the output of phase comparator 1. This also causes the VCO to oscillate at the centre frequency (fo). The frequency capture range (2 fc) is defined as the frequency range of input signals on which the PLL will lock if it was initially out of lock. The frequency lock range (2 fL) is defined as the frequency range of input signals on which the loop will stay locked if it was initially in lock. The capture range is smaller or equal to the lock range. With phase comparator 1, the range of frequencies over which the PLL can acquire lock (capture range) depends on the low-pass filter characteristics and this range can be made as large as the lock range. Phase comparator 1 enables the PLL system to remain in lock in spite of high amounts of noise in the input signal. A typical behaviour of this type of phase comparator is that it may lock onto input frequencies that are close to harmonics of the VCO centre frequency. Another typical behaviour is, that the phase angle between the signal and comparator input varies between 0° and 180° and is 90° at the centre frequency. Figure 3 shows the typical phase-to-output response characteristic. Philips Semiconductors Product specification Phase-locked loop HEF4046B MSI (1) Average output voltage. Fig.3 Signal-to-comparator inputs phase difference for comparator 1. Figure 4 shows the typical waveforms for a PLL employing phase comparator 1 in locked condition of fo. Fig.4 Typical waveforms for phase-locked loop employing phase comparator 1 in locked condition of fo. January 1995 4 Philips Semiconductors Product specification Phase-locked loop Phase comparator 2 is an edge-controlled digital memory network. It consists of four flip-flops, control gating and a 3-state output circuit comprising p and n-type drivers having a common output node. When the p-type or n-type driv.


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