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4066B Dataheets PDF



Part Number 4066B
Manufacturers NXP
Logo NXP
Description Quadruple bilateral switches
Datasheet 4066B Datasheet4066B Datasheet (PDF)

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4066B gates Quadruple bilateral switches Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple bilateral switches DESCRIPTION The HEF4066B has four independent bilateral analogue switches (transmission gates).

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4066B gates Quadruple bilateral switches Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple bilateral switches DESCRIPTION The HEF4066B has four independent bilateral analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to VDD a low impedance bidirectional path between Y and Z is established (ON condition). When E is connected to VSS the switch is HEF4066B gates disabled and a high impedance between Y and Z is established (OFF condition). The HEF4066B is pin compatible with the HEF4016B but exhibits a much lower ON resistance. In addition the ON resistance is relatively constant over the full input signal range. Fig.1 Functional diagram. Fig.2 Pinning diagram. PINNING HEF4066BP(N): 14-lead DIL; plastic (SOT27-1) HEF4066BD(F): 14-lead DIL; ceramic (cerdip) (SOT73)) HEF4066BT(D): 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America APPLICATION INFORMATION An example of application for the HEF4066B is: • Analogue and digital switching E0 to E3 Y0 to Y3 Z0 to Z3 enable inputs input/output terminals input/output terminals Fig.3 Schematic diagram (one switch). January 1995 2 Philips Semiconductors Product specification Quadruple bilateral switches RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Power dissipation per switch For other RATINGS see Family Specifications DC CHARACTERISTICS Tamb = 25 °C VDD V 5 ON resistance 10 15 5 ON resistance 10 15 5 ON resistance ‘∆’ ON resistance between any two channels OFF state leakage current, any channel OFF En input voltage LOW 10 15 5 10 15 5 10 15 5 10 15 VIL IOZ ∆RON RON RON RON SYMBOL MIN. − − − − − − − − − − − − − − − − − − − − − 2,25 4,50 6,75 TYP. MAX. 350 80 60 115 50 40 120 65 50 25 10 5 2500 Ω 245 Ω 175 Ω 340 Ω 160 Ω 115 Ω 365 Ω 200 Ω 155 Ω − − − − − Ω Ω Ω nA nA 1 V 2 V 2 V En at VSS P max. HEF4066B gates 100 mW CONDITIONS En at VDD Vis = VSS to VDD see Fig.4 En at VDD Vis = VSS see Fig.4 En at VDD Vis = VDD see Fig.4 En at VDD Vis = VSS to VDD see Fig.4 200 nA Iis = 10 µA see Fig.9 VDD V SYMBOL −40 Tamb (°c) +25 +85 MAX. 7,5 µA 15,0 µA 30,0 µA 1000 nA CONDITIONS MAX. MAX. Quiescent device current Input leakage current at En 5 10 15 15 ± IIN IDD 1,0 2,0 4,0 − 1,0 2,0 4,0 300 VSS = 0; all valid input combinations; VI = VSS or VDD En at VSS or VDD January 1995 3 Philips Semiconductors Product specification Quadruple bilateral switches HEF4066B gates Fig.4 Test set-up for measuring RON. En at VDD Iis = 200 µA VSS = 0 V Fig.5 Typical RON as a function of input voltage. NOTE To avoid drawing VDD current out of terminal Z, when switch current flows into.


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