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Hex Inverter. 4069UB Datasheet

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Hex Inverter. 4069UB Datasheet






4069UB Inverter. Datasheet pdf. Equivalent




4069UB Inverter. Datasheet pdf. Equivalent





Part

4069UB

Description

Hex Inverter



Feature


MC14069UB Hex Inverter The MC14069UB he x inverter is constructed with MOS P− channel and N−channel enhancement mod e devices in a single monolithic struct ure. These inverters find primary use w here low power dissipation and/or high noise immunity is desired. Each of the six inverters is a single stage to mini mize propagation delays. Features • S upply Voltage Range = 3..
Manufacture

ON Semiconductor

Datasheet
Download 4069UB Datasheet


ON Semiconductor 4069UB

4069UB; 0 Vdc to 18 Vdc • Capable of Driving T wo Low−Power TTL Loads or One Low−P ower Schottky TTL Load Over the Rated T emperature Range • Triple Diode Prote ction on All Inputs • Pin−for−Pin Replacement for CD4069UB • Meets JED EC UB Specifications • NLV Prefix for Automotive and Other Applications Requ iring Unique Site and Control Change Re quirements; AEC−Q100 Qualified and P.


ON Semiconductor 4069UB

PAP Capable • These Devices are Pb−F ree and are RoHS Compliant MAXIMUM RAT INGS (Voltages Referenced to VSS) Symb ol Parameter Value Unit VDD Vin, Vo ut DC Supply Voltage Range Input or Ou tput Voltage Range (DC or Transient) 0.5 to +18.0 V −0.5 to VDD + 0.5 V Iin, Iout Input or Output Current ( DC or Transient) per Pin ±10 mA PD Power Dissipation, per Pack.


ON Semiconductor 4069UB

age (Note 1) 500 mW TA Ambient Tempe rature Range Tstg Storage Temperature Range −55 to +125 °C −65 to +15 0 °C TL Lead Temperature (8−Seco nd Soldering) 260 °C Stresses excee ding those listed in the Maximum Rating s table may damage the device. If any o f these limits are exceeded, device fun ctionality should not be assumed, damag e may occur and reliability.

Part

4069UB

Description

Hex Inverter



Feature


MC14069UB Hex Inverter The MC14069UB he x inverter is constructed with MOS P− channel and N−channel enhancement mod e devices in a single monolithic struct ure. These inverters find primary use w here low power dissipation and/or high noise immunity is desired. Each of the six inverters is a single stage to mini mize propagation delays. Features • S upply Voltage Range = 3..
Manufacture

ON Semiconductor

Datasheet
Download 4069UB Datasheet




 4069UB
MC14069UB
Hex Inverter
The MC14069UB hex inverter is constructed with MOS P−channel
and N−channel enhancement mode devices in a single monolithic
structure. These inverters find primary use where low power
dissipation and/or high noise immunity is desired. Each of the six
inverters is a single stage to minimize propagation delays.
Features
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low−Power TTL Loads or One
Low−Power Schottky TTL Load Over the Rated Temperature
Range
Triple Diode Protection on All Inputs
Pin−for−Pin Replacement for CD4069UB
Meets JEDEC UB Specifications
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
MAXIMUM RATINGS (Voltages Referenced to VSS)
Symbol
Parameter
Value
Unit
VDD
Vin, Vout
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
−0.5 to +18.0
V
−0.5 to VDD + 0.5
V
Iin, Iout Input or Output Current
(DC or Transient) per Pin
±10
mA
PD Power Dissipation, per Package
(Note 1)
500
mW
TA
Ambient Temperature Range
Tstg Storage Temperature Range
−55 to +125
°C
−65 to +150
°C
TL
Lead Temperature
(8−Second Soldering)
260
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, Vin and Vout should be constrained
to the range VSS (Vin or Vout) VDD.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either VSS or VDD). Unused outputs must be left open.
http://onsemi.com
SOIC−14
D SUFFIX
CASE 751A
SOEIAJ−14
F SUFFIX
CASE 965
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
IN 1 1
OUT 1 2
IN 2 3
OUT 2 4
IN 3 5
OUT 3 6
VSS 7
14 VDD
13 IN 6
12 OUT 6
11 IN 5
10 OUT 5
9 IN 4
8 OUT 4
MARKING DIAGRAMS
14
14069UG
AWLYWW
1
SOIC−14
14
MC14069UB
ALYWG
1
SOEIAJ−14
14
14
069U
ALYWG
G
1
TSSOP−14
A
WL, L
YY, Y
WW, W
G or G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
© Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 11
Publication Order Number:
MC14069UB/D




 4069UB
MC14069UB
1
2
3
4
VDD = PIN 14
VSS = PIN 7
5
6
9
8
11
10
13
12
Figure 1. Logic Diagram
INPUT*
VDD
OUTPUT
VSS
*Double diode protection on all inputs not shown
(1/6 of circuit shown)
Figure 2. Circuit Schematic
PULSE
GENERATOR
VDD
14 OUTPUT
INPUT
7 VSS
CL
20 ns
INPUT
tPHL
OUTPUT
90%
50%
10%
90%
50%
10%
tTHL
Figure 3. Switching Time Test Circuit and Waveforms
20 ns
VDD
VSS
tPLH
VOH
tTLH
VOL
ORDERING INFORMATION
Device
Package
Shipping
MC14069UBDG
SOIC−14
(Pb−Free)
55 Units / Rail
NLV14069UBDG*
SOIC−14
(Pb−Free)
55 Units / Rail
MC14069UBDR2G
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
NLV14069UBDR2G*
SOIC−14
(Pb−Free)
2500 Units / Tape & Reel
MC14069UBDTR2G
TSSOP−14
(Pb−Free)
2500 Units / Tape & Reel
NLV14069UBDTR2G*
TSSOP−14
(Pb−Free)
2500 Units / Tape & Reel
MC14069UBFELG
SOEIAJ−14
(Pb−Free)
2000 Units / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
http://onsemi.com
2




 4069UB
MC14069UB
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
−55_C
25_C
125_C
Characteristic
VDD
Typ
Symbol Vdc Min
Max
Min (Note 2) Max
Min
Max Unit
Output Voltage
Vin = VDD
“0” Level VOL
5.0
0.05
10
0.05
15
0.05
0
0.05
0.05 Vdc
0
0.05
0.05
0
0.05
0.05
Vin = 0
“1” Level VOH
5.0 4.95
4.95
5.0
10 9.95
9.95
10
15 14.95
14.95
15
4.95
Vdc
9.95
14.95
Input Voltage
(VO = 4.5 Vdc)
(VO = 9.0 Vdc)
(VO = 13.5 Vdc)
(VO = 0.5 Vdc)
(VO = 1.0 Vdc)
(VO = 1.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Input Current
Input Capacitance
(Vin = 0)
Quiescent Current
(Per Package)
“0” Level VIL
“1” Level VIH
IOH
Source
Sink IOL
Iin
Cin
IDD
Vdc
5.0
1.0
2.25
1.0
1.0
10
2.0
4.50
2.0
2.0
15
2.5
6.75
2.5
2.5
5.0
4.0
4.0
2.75
10
8.0
8.0
5.50
15 12.5
12.5
8.25
Vdc
4.0
8.0
12.5
5.0 –3.0
–2.4
–4.2
5.0 –0.64
–0.51 –0.88
10 –1.6
–1.3
–2.25
15 –4.2
–3.4
–8.8
mAdc
–1.7
–0.36
–0.9
–2.4
5.0 0.64
0.51
0.88
10
1.6
1.3
2.25
15
4.2
3.4
8.8
0.36
− mAdc
0.9
2.4
15
±0.1
±0.00001 ±0.1
±1.0 mAdc
5.0
7.5
pF
5.0
0.25
0.0005 0.25
10
0.5
0.0010
0.5
15
1.0
0.0015
1.0
7.5 mAdc
15
30
Total Supply Current (Notes 3 and 4)
IT
5.0
(Dynamic plus Quiescent,
10
Per Gate) (CL = 50 pF)
15
IT = (0.3 mA/kHz) f + IDD/6
IT = (0.6 mA/kHz) f + IDD/6
IT = (0.9 mA/kHz) f + IDD/6
mAdc
Output Rise and Fall Times (Note 3)
tTLH,
ns
(CL = 50 pF)
tTHL
5.0
100
200
tTLH, tTHL = (1.35 ns/pF) CL + 33 ns
10
50
100
tTLH, tTHL = (0.60 ns/pF) CL + 20 ns
15
40
80
tTLH, tTHL = (0.40 ns/pF) CL + 20 ns
Propagation Delay Times (Note 3)
tPLH,
(CL = 50 pF)
tPHL
tPLH, tPHL = (0.90 ns/pF) CL + 20 ns
5.0
tPLH, tPHL = (0.36 ns/pF) CL + 22 ns
10
tPLH, tPHL = (0.26 ns/pF) CL + 17 ns
15
65
125
40
75
30
55
ns
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.
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3



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