Triple 3-input AND gate
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
• The IC04 LOCMOS HE4000B Logic Family ...
Description
INTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4073B gates Triple 3-input AND gate
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
Triple 3-input AND gate
DESCRIPTION The HEF4073B provides the positive triple 3-input AND function. The outputs are fully buffered for highest noise immunity and pattern insensitivity of output impedance.
HEF4073B gates
Fig.2 Pinning diagram.
HEF4073BP(N): 14-lead DIL; plastic (SOT27-1) HEF4073BD(F): 14-lead DIL; ceramic (cerdip) (SOT73) HEF4073BT(D): 14-lead SO; plastic Fig.1 Functional diagram. (SOT108-1) ( ): Package Designator North America
Fig.3 Logic diagram (one gate).
FAMILY DATA, IDD LIMITS category GATES See Family Specifications
January 1995
2
Philips Semiconductors
Product specification
Triple 3-input AND gate
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times ≤ 20 ns VDD V Propagation delays In → On HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 55 25 20 45 20 15 60 30 20 60 30 20 110 50 40 90 40 30 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX.
HEF4073B gates
TYPICAL EXTRAPOLATION FORMULA 23 ns + (0,55 ns/pF) CL 14 ns + (0,23 ns/pF) CL 12 ns + (0,16 ns/pF) C...
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