LV74

INTEGRATED CIRCUITS 74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger Product specification Supersedes data of 1996 Nov 07 IC24 Data Handbook 1998 Apr 20 Philips Semiconductors Philips Semiconductors Product specification Dual D-type flip-flop with set and reset; positive edge-trigger 74LV74 FEATURES Wide operating voltage: 1.0 to 5.5V Optimized for Low Voltage applications: 1.0 to 3.6V Accepts TTL input levels between VCC = 2.7V and VCC = 3.6V Typical VOLP (output ground bounce) t 0.8V @ VCC = 3.3V, Typical VOHV (output VOH undershoot) u 2V @ VCC = 3.3V, Output capability: standard ICC category: flip-flops QUICK REFERENCE DATA GND = 0V; Tamb = 25°C; tr =tf v2.5 ns SYMBOL PARAMETER tPHL/tPLH Propagation delay nCP to nQ, nQ nSD to nQ, nQ nRD to nQ, nQ Maximum clock frequency Input capacitance Power dissipation capacitance per flip-flop Tamb = 25°C Tamb = 25°C DESCRIPTION The 74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. The 74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition,...