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M-986-2A1P Dataheets PDF



Part Number M-986-2A1P
Manufacturers Clare Inc.
Logo Clare  Inc.
Description MF Transceiver
Datasheet M-986-2A1P DatasheetM-986-2A1P Datasheet (PDF)

M-986-2A1 MF Transceiver Features • Direct A-Law or µ-Law PCM digital input • 2.048 Mb/s clocking • Operates with standard codecs for analog interfacing • Microprocessor read/write interface • Binary or 2-of-6 data formats • Dual-channel • 5 volt power Description The M-986-2A1 dual channel MF Transceiver contains all the logic necessary to transmit and receive (North American) CCITT Region 1 multifrequency signals on one integrated circuit (IC). Operating with a 20.48 MHz crystal, the M-986 is .

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M-986-2A1 MF Transceiver Features • Direct A-Law or µ-Law PCM digital input • 2.048 Mb/s clocking • Operates with standard codecs for analog interfacing • Microprocessor read/write interface • Binary or 2-of-6 data formats • Dual-channel • 5 volt power Description The M-986-2A1 dual channel MF Transceiver contains all the logic necessary to transmit and receive (North American) CCITT Region 1 multifrequency signals on one integrated circuit (IC). Operating with a 20.48 MHz crystal, the M-986 is capable of providing a direct digital interface to a mlaw or A-law encoded PCM digital input. Each channel can be connected to an analog source using a coderdecoder (codec) as shown in the Block Diagram below. The M-986 is configured and controlled through an integral coprocessor port. Applications • • • • • Test equipment Trunk adapters Paging terminals Traffic recorders PBXs Ordering Information Part # M-986-2A1P M-986-2A1PL Description 40-pin plastic DIP 44-pin PLCC Block Diagram DS-M986-2A1 www.clare.com 1 M-986-2A1 Absolute Maximum Ratings Over Specified Temperature Range Supply voltage range, VCC Input voltage range Output voltage range Ambient air temperature range Storage temperature range -0.3 V to 7 V -0.3 V to 15 V -0.3 V to 15 V 0˚ to 150˚C -45˚C to 150˚C Absolute Maximum Ratings are stress ratings. Stresses in excess of these ratings can cause permanent damage to the device. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this data sheet is not implied. Exposure of the device to the absolute maximum ratings for an extended period may degrade the device and effect its reliability. Function Description The M-986-2A1 can be set up for various modes of operation by writing two configuration bytes to the coprocessor port. The format of the two configuration bytes is shown in the Configuration Table on page 3 and the configuration options are described in the following paragraphs. Configuration Options External/Internal Codec Clock (ECLK): If external codec clocking is selected, an external clocking source provides an 8 kHz transmit framing clock and an 8 kHz receive framing clock. It also provides a serial bit clock with a frequency that is a multiple of 8 kHz between 216 kHz and 2.496 MHz for exchange of data via the serial ports. When internal codec clocking is selected, the M-986-2A1 provides an 8 kHz framing clock and a 2.048 MHz serial bit clock. 2 of 6/Binary Input/Output (IOM): When the 2-of-6 input/output is selected, the M-986-2A1 encodes the received R1 MF tone pair into a 6-bit format, where each bit represents one of the six possible frequencies. A logic high level indicates the presence of a frequency. The digital input to the M-986-2A1 that selects the transmitted R1 MF tone pair must also be coded in the 2-of-6 format. Electrical Characteristics/Temperature Range When binary input/output is selected, the M-986-2A1 encodes the received R1 MF tone pair into a 4 bit binary format. The digital input to the M-986-2A1 that selects the transmitted R1 MF tone pair must also be coded in a 4 bit binary format. Enable/Disable Channel (ENC): When a channel is disabled, the receiver does not process its codec input for R1 MF tones, and the transmitter does not respond to transmit commands. If a transmit command is given while the channel is enabled, the “tone off” command must be given before the channel is disabled. Disabling the channel does not automatically shut off the transmitter. When a channel is enabled, the receiver and transmitter for that channel function normally. Long/Short KP Tone Detection Time (KPL): When long KP tone detection is selected, the minimum on time for the KP tone to be detected is 55 milliseconds. When short KP tone detection is selected, the minimum on time for the KP tone to be detected is 30 milliseconds (the same as the minimum on time for the rest of the MF tones). Enable MF Tone Detection After Reception of KP (KPEN): When this feature is enabled, MF tone detection is enabled after reception of the KP tone, and disabled after reception of ST, ST1, ST2, or ST3 tones. When this feature is disabled, MF tone detection is always enabled. Select A or µ-law input/output (AMU) for A-law encoding, this bit is set to a 1, for µ-law encoding it is set to 0. Typ 2.4 VCC -0.4 Max 50 3 0.3 25 15 25 10 Unit 75 0.6 20 -20 ±20 ±50 - ICC VOH VOL IOZ II CI CO Parameter Test ConditionsMin Supply current f = 20.5 MHz, VCC = 5.5V, TA = 0˚ to 70 ˚C High-level output voltage IOH = MAX IOH = 20 µ A Low-level output voltage IOL = MAX Off-state output current VCC = MAX VO = 2.4 V VO = 0.4 V Input current VI = VSS to VCC Except CLKIN CLKIN Input capacitance Data bus f = 1 MHz, all other pins 0 V All others Output capacitance Data bus All others mA V V V µA µA µA µA pF pF pF pF Rev. 3 2 www.clare.com M-986-2A1 Configuration Configuration Byte 1 Bit 7 0 ECLK IOM ENC1 KPL1 KPEN1 Bit 6 0 Bit 5 ECLK Channels 1 & 2 C.


M-986-2A1 M-986-2A1P M-986-2A1PL


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