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M-986-2R2PL Dataheets PDF



Part Number M-986-2R2PL
Manufacturers Clare Inc.
Logo Clare  Inc.
Description MFC Transceivers
Datasheet M-986-2R2PL DatasheetM-986-2R2PL Datasheet (PDF)

M-986-2R2 MFC Transceivers Features • Direct A-Law PCM digital input • 2.048 Mb/s clocking • Programmable forward/backward mode • Programmable compelled/direct control • Operates with standard codecs for analog interfacing • Microprocessor read/write interface • Binary or 2-of-6 data formats • Single- or dual-channel versions • 5 volt power Applications • Test equipment • Trunk adapters • Paging terminals • Traffic recorders • PBXs Description The M-986-1R2 and -2R2 MFC Transceivers contain all .

  M-986-2R2PL   M-986-2R2PL



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M-986-2R2 MFC Transceivers Features • Direct A-Law PCM digital input • 2.048 Mb/s clocking • Programmable forward/backward mode • Programmable compelled/direct control • Operates with standard codecs for analog interfacing • Microprocessor read/write interface • Binary or 2-of-6 data formats • Single- or dual-channel versions • 5 volt power Applications • Test equipment • Trunk adapters • Paging terminals • Traffic recorders • PBXs Description The M-986-1R2 and -2R2 MFC Transceivers contain all the logic necessary to transmit and receive CCITT R2F (forward) and R2B (backward) multifrequency signals on one 40-pin integrated circuit (IC). M-9861R2 is a single-channel version; M-986-2R2 provides two channels. R1 single and dual multifrequency transceivers are also available as M-986-1R1 and 2R1. Operating with a 20.48 MHz crystal, the M-986 is capable of providing a direct digital interface to an Alaw-encoded PCM digital input. Each channel can be connected to an analog source using a coder-decoder (codec) as shown in the Block Diagram below. The M-986 can be configured by the customer to operate with the transmitter and receiver either coupled together or independently, allowing it to handle a compelled cycle automatically or via command from the host processor. For the R2 versions of the M-986, A-law is used for coding/decoding. The M-986 is configured and controlled through an integral coprocessor port. Pin Assignments Ordering Information Part # M-986-1R2P M-986-1R2PL M-986-2R2P M-986-2R2PL Description 40-pin plastic DIP, Single Channel 44-pin PLCC, Single Channel 40-pin plastic DIP, Dual Channel 44-pin PLCC, Dual Channel Block Diagram DS-M976-2R2-R3 www.clare.com 1 M-986-2R2 Function Description The M-986 can be set up for various operating modes by writing two configuration bytes to the coprocessor port. Configuration Options External/Internal Codec Clock (ECLK): If external codec clocking is selected, an external clocking source provides an 8kHz transmit framing clock and an 8kHz receive framing clock. It also provides a serial bit clock with a frequency that is a multiple of 8 kHz between 2.496 MHz and 216 kHz for exchange of data via the serial ports. When internal codec clocking is selected, the M-986 provides an 8kHz framing clock and a 2.048 MHz serial bit clock. Binary/2 of 6 Input/Output (IOM): When the 2-of-6 input/output is selected, the M-986 encodes the received R2 MF tone pair into in a 6-bit format, where each bit represents one of the six possible frequencies. A logic high level indicates the presence of a frequency. The digital input to the M-986 that selects the transmitted R2 MF tone pair must also be coded in the 2-of-6 format. When binary input/output is selected, the M-986 encodes the received R2 MF tone pair into a 4 bit binary format. The digital input to the M-986 that selects the transmitted R2 MF tone pair must also be coded in a 4 bit binary format. Configuration Bytes Configuration Byte 1 Bit 7 0 ECLK IOM ENC.


M-986-2R2P M-986-2R2PL M-991


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