M2086

Integrated Circuit Systems, Inc. Preliminary Information VCSO FEC PLL WITH AUTOSWITCH FOR SONET/OTN PIN ASSIGNMENT (9 x 9 mm SMT) FIN_SEL1 GND P_SEL2 DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 FEC_SEL0 FEC_SEL1 LOL NBW VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19 M2080/81/82 M2085/86/87 GENERAL DESCRIPTION The M2080/81/82 and M2085/86/87 are VCSO (Voltage Controlled SAW Oscillator) based clock PLLs designed for FEC clock ratio translation in 10Gb optical systems such as OC-192 or 10GbE. They support FEC (Forward Error Correction) clock multiplication ratios, both forward (mapping) and inverse (de-mapping). Multiplication ratios are pin-selected from pre-programming look-up tables. FEATURES ◆ Integrated SAW delay line; Output of 15 to 700 MHz * ◆ Low phase jitter < 0.5 ps rms typical (12kHz to 20MHz or 50kHz to 80MHz) ◆ LVPECL clock output (CML and LVDS options available) ◆ Pin-selectable PLL divider ratios support FEC ratios M2080/85: OTU1 (255/238) and OTU2 (255/237) Mapping M2081/86: OTU1 (238/255) or OTU2 (237/255) De-mapping M2082/87: OTU1 (238/255) and OTU2 (237/255) De-mapping 28 29 30 31 32 33 34 35 36 M2080 Series (Top View) 18 17 16 15 14 13 12 11 10 P_SEL0 P_SEL1 nFOUT FOUT GND REF_ACK AUTO VCC GND Figure 1: Pin Assignment Example I/O Clock Frequency Combinations Using M2081-11-622.0800 FEC De-Map Ratios FEC De-Map PLL Ratio Mfec / Rfec 1/1 237/255 238/255 Base Input Rate 1 (MHz) 622.0800 666.5143 669.3266 Output Clock (either output) ...