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FHX35X Dataheets PDF



Part Number FHX35X
Manufacturers Fujitsu Media Devices Limited
Logo Fujitsu Media Devices Limited
Description Low Noise HEMT
Datasheet FHX35X DatasheetFHX35X Datasheet (PDF)

FHX35X/002 FHX35LG/002 Low Noise HEMT DESCRIPTION The FHX35X/002 Chip and FHX35LG/002 packaged devices are HEMT (High Electron Mobility Transistor) ones suitable for use as the front end of an optical receiver in high speed lightwave communication systems. This HEMT combines high transconductance, low gate capacitance and low leakage current; all important factors in achieving low noise preamplification. Fujitsu’s stringent Quality Assurance criteria and detailed Test Procedures assure Highest R.

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FHX35X/002 FHX35LG/002 Low Noise HEMT DESCRIPTION The FHX35X/002 Chip and FHX35LG/002 packaged devices are HEMT (High Electron Mobility Transistor) ones suitable for use as the front end of an optical receiver in high speed lightwave communication systems. This HEMT combines high transconductance, low gate capacitance and low leakage current; all important factors in achieving low noise preamplification. Fujitsu’s stringent Quality Assurance criteria and detailed Test Procedures assure Highest Reliabiltity Performance. FEATURES • • • • • High Transconductance Low Leakage Current Low Gate Capacitance Gold Bonding System Proven Reliability LG PACKAGE ABSOLUTE MAXIMUM RATINGS (Ambient Temperature Ta=25°C) Item Drain-Source Voltage Gate-Source Voltage Total Power Dissipation Storage Temperature Channel Temperature Thermal Resistance Symbol VDS VGS PT Tstg Tch Rth Channel to Case Conditions Ratings 6 -5 290 -65 to 175 +175 150 Unit V V mW °C °C °C/W ELECTRICAL CHARACTERISTICS (Ambient Temperature Ta=25°C) Item Drain Current Transconductance Pinch-off Voltage Gate-Source Leakage Current Gate-Source Capacitance Gate-Drain Capacitance Symbol IDSS gm Vp IGSO CGS CGD Conditions VDS=2V, VGS=0V VDS=2V, IDS=10mA VDS=2V, IDS=1mA VGS=-2V VDS=3V IDS=10mA FHX35X/002 FHX35LG/002 Min. 15 45 -0.2 Limits Min. 40 60 -1.0 10 0.27 0.47 0.035 Max. 85 -2.0 20 pF Unit mA mS V nA pF VDS=3V, IDS=10mA Edition 1.1 May 1998 1 FHX35X/002 FHX35LG/002 Low Noise HEMT Fig. 1 Drain Current vs. Drain-Source Voltage Fig. 2 Gate-Source Capacitance vs. Drain-Source Current VDS=3V 40 Drain Current (mA) Gate-Source Capacitance (pF) VGS=0V -0.2V 0.5 FHX35LG/002 0.4 30 -0.4V 20 -0.6V 10 -0.8V 0 -1.0V 1 2 3 0.3 FHX35X/002 0.2 10 20 30 Drain-source Voltage (V) Drain-Source Current (mA) Fig. 3 Transconductance vs. Gate-Source Voltage Gate-Source Leakage Current (mA) Fig. 4 Gate-Source Leakage Current vs. Gate-Source Voltage VDS=2V Transconductance (mS) 80 50 60 20 10 5 40 20 0 -0.2 -0.4 -0.6 -0.8 0 -1.0 -2.0 -3.0 Gate-Source Voltage (V) Gate-Source Voltage (V) 2 FHX35X/002 FHX35LG/002 Low Noise HEMT BONDING PROCEDURE FOR FET CHIPs Caution must be excercised to prevent static build up by proper grounding of all equipment and personnel. All operations must be performed in a clean, dust-free and dry environment. 1. Storage Condition: Store in a clean, dry nitrogen environment. 2. Die-Attach 2.1 The die-attach station must have an accurate temperature control, and an inert forming gas should be used. 2.2 Chips should be kept at room temperature, except during die-attach. 2.3 Place package or carrier on the heated stage. 2.4 Place the solder at the position where the chip will be bonded. 2.5 Lightly grasp the chip edges using tweezers and scrub the die onto the Au-Sn solder preform. The die attach conditions are: 300 to 310° for 30 to 60 seconds. The Au-Sn (80-20) solder preform volume should be about 3.2x10-3 mm3 for FHX35X/002. 3. Wire Bonding 3.1 Bonding C.


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