Document
November 1997
FDC6322C Dual N & P Channel , Digital FET
General Description
These dual N & P Channel logic level enhancement mode field effec transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors.
Features
N-Ch 25 V, 0.22 A, RDS(ON) = 5 Ω @ VGS= 2.7 V. P-Ch 25 V, -0.46 A, RDS(ON) = 1.5 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits. VGS(th) < 1.5 V. Gate-Source Zener for ESD ruggedness. >6kV Human Body Model Replace NPN & PNP digital transistors.
SOT-23
SuperSOTTM-6 Mark: .322
SuperSOTTM-8
SO-8
SOT-223
SOIC-16
4
3
5
2
6
1
Absolute Maximum Ratings
Symbol VDSS, VCC VGSS, VIN ID, IO PD TJ,TSTG ESD Parameter
TA = 25oC unless other wise noted N-Channel 25 8 P-Channel -25 -8 -0.46 -1 0.9 0.7 -55 to 150 6 °C kV W Units V V A
Drain-Source Voltage, Power Supply Voltage Gate-Source Voltage, Drain/Output Current - Continuous - Pulsed Maximum Power Dissipation
(Note 1a) (Note 1b)
0.22 0.5
Operating and Storage Tempature Ranger Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf / 1500 Ohm)
THERMAL CHARACTERISTICS RθJA RθJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)
140 60
°C/W °C/W
© 1997 Fairchild Semiconductor Corporation
FDC6322C.Rev B1
DMOS Electrical Characteristics (TA = 25 OC unless otherwise noted )
Symbol Parameter Conditions
Type
N-Ch P-Ch N-Ch P-Ch N-Ch TJ = 55°C
Min
Typ
Max
Units
OFF CHARACTERISTICS BVDSS Drain-Source Breakdown Voltage VGS = 0 V, ID = 250 µA VGS = 0 V, ID = -250 µA ID= 250 µA, Referenced to 25 oC ID = -250 µA, Referenced to 25 oC IDSS IDSS IGSS Zero Gate Voltage Drain Current VDS= 20 V, VGS= 0 V, VDS =-20 V, VGS = 0 V, TJ = 55°C Gate - Body Leakage Current VGS = 8 V, VDS= 0 V VGS = -8 V, VDS= 0 V ON CHARACTERISTICS (Note 2) N-Ch P-Ch 25 -25 25 -22 1 10 P-Ch -1 -10 100 -100 nA nA mV / oC µA µA mV /oC V
∆BVDSS/∆TJ
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
∆VGS(th)/∆TJ
VGS(th) RDS(ON)
Gate Threshold Voltage Temp. Coefficient
ID = 250 µA, Referenced to 25 o C ID= -250 µA, Referenced to 25 C
o
N-Ch P-Ch N-Ch P-Ch N-Ch 0.65 -0.65
-2.1 2.1 0.85 -0.86 3.8 6.3 3.1 1.5 -1.5 5 9 4 1.5 2.4 1.1
Gate Threshold Voltage
VDS = VGS, ID= 250 µA VDS = VGS, ID= -250 µA VGS = 2.7 V, ID = 0.2 A TJ =125°C VGS = 4.5 V, ID = 0.4 A VGS = -2.7 V, ID = -0.25 A TJ =125°C VGS = -4.5 V, ID = -0.5 A
V
Static Drain-Source On-Resistance
Ω
P-Ch
1.22 1.65 0.87
ID(ON) gFS
On-State Drain Current
VGS = 2.7 V, VDS = 5 V VGS = -2.7 V, VDS = -5 V VDS = 5 V, ID= 0.4 A VDS = -5 V, ID= -0.5 A
N-Ch P-Ch N-Ch P-Ch
0.2 -0.5 0.2 0.8
A
Forward Transconductance
S
DYNAMIC CHARACTERISTICS Ciss Coss Crss Input Capacitance N-Channel VDS= 10 V, VGS= 0 V, Output Capacitance Reverse Transfer Capacitance f = 1.0 MHz P-Channel VDS= -10 V, VGS = 0V, f = 1.0 MHz N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 9.5 62 6 35 1.3 9.5 pF
FDC6322C.Rev B1
SWITCHING CHARACTERISTICS (Note 2) Symbol tD(on) tr Parameter Turn - On Delay Time Conditions N-Channel VDD = 6 V, ID = 0.5 A, Turn - On Rise Time VGs = 4.5 V, RGEN = 50 Ω P-Channel VDD = -6 V, ID = -0.5 A, tf Turn - Off Fall Time VGen = -4.5 V, RGEN = 50 Ω N-Channel VDS= 5 V, ID = 0.2 A, Qgs Qgd Gate-Source Charge VGS = 4.5 V P- Channel Gate-Drain Charge VDS = -5 V, ID = -0.25 A, VGS = -4.5 V DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS IS VSD Maximum Continuous Drain-Source Diode Forward Current N-Ch P-Ch Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.5 A VGS = 0 V, IS = -0.5 A
(Note 2) (Note 2)
Type
N-Ch P-Ch N-Ch P-Ch
Min
Typ 5 7 4.5 8 4 55 3.2 35 0.49 1 0.22 0.32 0.07 0.25
Max 10 14 10 16 8 90 7 55 0.7 1.5
Units nS
nS
tD(off)
Turn - Off Delay Time
N-Ch P-Ch N-Ch P-Ch
nS
nS
Qg
Total Gate Charge
N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch
nC
nC
nC
0.5 -0.5 0.97 -0.88 1.3 -1.2
A
N-Ch P-Ch
V
Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. RθJA shown below for single device operation on FR-4 in still air.
a. 140OC/W on a 0.125 in2 pad of 2oz copper.
b. 180OC/W on a 0.005 in2 of pad of 2oz copper.
Scale 1 : 1 on letter size paper 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDC6322C.Rev B1
Typical Electrical Characteristics: N-Channel
0.5
4.0 3.5 3.0 2.7
R DS(on) , NORMALIZED DRAIN-SOURCE ON-RESISTANCE
V GS = 4.5V
1.4
I D , DRAIN-SOURCE CURRENT (A)
0.4
VGS = 2.0V
1.2
.