FDC654P

March 1998 FDC654P P-Channel Enhancement Mode Field Effect Transistor General Description These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as cellular phone and notebook computer power management and other battery powered circuits where high-side switching, and low in-line power loss are needed in a very small outline surface mount package. Features -3.6 A, -30 V. RDS(ON) = 0.075 Ω @ VGS = -10 V RDS(ON) = 0.125 Ω @ VGS = -4.5 V. SuperSOTTM-6 package design using copper lead frame for superior thermal and electrical capabilities. High density cell design for extremely low RDS(ON). Exceptional on-resistance and maximum DC current capability. SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 SOIC-16 S D D 1 6 4 .65 G pin 1 2 5 D D SuperSOT TM -6 3 4 Absolute Maximum Ratings T A = 25°C unless otherwise note Symbol Parameter VDSS VGSS ID PD Drain-Source Voltage Gate-Source Voltage - Continuous Drain Current - Continuous - Pulsed Maximum Power Dissipation (Note 1a) (Note 1b) (Note 1a) FDC654P -30 ±20 -3.6 -10 1.6 0.8 -55 to 150 Units V V A W TJ,TSTG RθJA RθJC Operating and Storage Temperature Range °C THERMAL CHARACTERISTICS Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-C...