FET/ P-Channel. FDG314P Datasheet

FDG314P Datasheet PDF, Equivalent


Part Number

FDG314P

Description

Digital FET/ P-Channel

Manufacture

Fairchild Semiconductor

Total Page 5 Pages
PDF Download
Download FDG314P Datasheet PDF


FDG314P Datasheet
July 2000
FDG314P
Digital FET, P-Channel
General Description
This P-Channel enhancement mode field effect
transistor is produced using Fairchild Semiconductor’s
proprietary, high cell density, DMOS technology. This
very high density process is tailored to minimize on-
state resistance at low gate drive conditions. This
device is designed especially for battery power
applications such as notebook computers and cellular
phones. This device has excellent on-state resistance
even at gate drive voltages as low as 2.5 volts.
Applications
Power Management
Load switch
Signal switch
Features
-0.65 A, -25 V. RDS(ON) = 1.1 @ VGS = -4.5 V
RDS(ON) = 1.5 @ VGS = -2.7 V.
Very low gate drive requirements allowing direct
operation in 3V cirucuits (VGS(th) <1.5 V).
Gate-Source Zener for ESD ruggedness
(>6 kV Human Body Model).
Compact industry standard SC70-6 surface mount
package.
S
D
D
SC70-6
G
D
D
16
25
34
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol
Parameter
VDSS
VGSS
ID
PD
TJ, Tstg
ESD
Drain-Source Voltage
Gate-Source Voltage
Drain Current - Continuous
- Pulsed
(Note 1a)
Power Dissipation for Single Operation
(Note 1a)
(Note 1b)
Operating and Storage Junction Temperature Range
Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100pf/1500 Ohm)
Ratings
-25
±8
-0.65
-1.8
0.75
0.48
-55 to +150
6.0
Thermal Characteristics
RθJA Thermal Resistance, Junction-to-Ambient
(Note 1b)
Package Marking and Ordering Information
Device Marking
Device
Reel Size
.14
FDG314P
7’’
260
Tape Width
8mm
Units
V
V
A
W
°C
kV
°C/W
Quantity
3000 units
2000 Fairchild Semiconductor International
FDG314P Rev.C

FDG314P Datasheet
Electrical Characteristics
Symbol
Parameter
TA = 25°C unless otherwise noted
Test Conditions
Min Typ Max Units
Off Characteristics
BVDSS
Drain-Source Breakdown Voltage VGS = 0 V, ID = -250 µA
-25
V
BVDSS
TJ
Breakdown Voltage Temperature ID = -250 µA, Referenced to 25°C
Coefficient
-19 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = -20 V, VGS = 0 V
-1 µA
IGSS
Gate-Body Leakage Current
VGS = -8 V, VDS = 0 V
-100 nA
On Characteristics (Note 2)
VGS(th)
Gate Threshold Voltage
VGS(th)
TJ
Gate Threshold Voltage
Temperature Coefficient
RDS(on)
Static Drain-Source
On-Resistance
ID(on)
gFS
On-State Drain Current
Forward Transconductance
VDS = VGS, ID = -250 µA
ID = -250 µA, Referenced to 25°C
VGS = -4.5 V, ID = -0.5 A
VGS = -4.5 V, ID = -0.5 A @ 125°C
VGS = -2.7 V, ID = -0.25 A
VGS = -4.5 V, VDS = -5 V
VDS = -4.5 V, ID = -0.5 A
-0.65 -0.72
2
0.77
1.08
1.06
-1
0.9
-1.5 V
mV/°C
1.1
1.8
1.5
A
S
Dynamic Characteristics
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
VDS = -10 V, VGS = 0 V,
f = 1.0 MHz
63 pF
34 pF
10 pF
Switching Characteristics
td(on)
Turn-On Delay Time
tr Turn-On Rise Time
td(off)
Turn-Off Delay Time
tf Turn-Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
Qgd Gate-Drain Charge
(Note 2)
VDD = -6 V, ID = -0.5 A,
VGS = -4.5 V, RGEN = 50
VDS = -5 V, ID = -0.25 A,
VGS = -4.5 V
7 20
8 20
55 110
35 70
1.1 1.5
0.32
0.25
ns
ns
ns
ns
nC
nC
nC
Drain-Source Diode Characteristics and Maximum Ratings
IS Maximum Continuous Drain-Source Diode Forward Current
-0.42
VSD
Drain-Source Diode Forward
VGS = 0 V, IS = -0.42 A
(Note 2)
Voltage
-0.85 -1.2
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface
of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
a) 170°C/W when mounted on a 1 in2 pad of 2oz copper.
b) 260°C/W when mounted on a minimum mounting pad.
2. Pulse Test: Pulse Width 300 µs, Duty Cycle 2.0%
A
V
FDG314P Rev.C


Features Datasheet pdf FDG314P July 2000 FDG314P Digital FET, P-Channel General Description This P-C hannel enhancement mode field effect tr ansistor is produced using Fairchild Se miconductor’s proprietary, high cell density, DMOS technology. This very hig h density process is tailored to minimi ze onstate resistance at low gate drive conditions. This device is designed es pecially for battery power applications such as notebook computers and cellula r phones. This device has excellent on- state resistance even at gate drive vol tages as low as 2.5 volts. Features -0.65 A, -25 V. RDS(ON) = 1.1 Ω @ V GS = -4.5 V RDS(ON) = 1.5 Ω @ VGS = - 2.7 V. • • • Very low gate driv e requirements allowing direct operatio n in 3V cirucuits (VGS(th) <1.5 V). Gat e-Source Zener for ESD ruggedness (>6 k V Human Body Model). Compact industry s tandard SC70-6 surface mount package. Applications • Power Management • L oad switch • Signal switch D D S 1 6 2 5 SC70-6 D D G 3 4 Absolute Maximum Ratings Symbol V DSS V GSS ID PD.
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