FDG314P

FDG314P July 2000 FDG314P Digital FET, P-Channel General Description This P-Channel enhancement mode field effect transistor is produced using Fairchild Semiconductor’s proprietary, high cell density, DMOS technology. This very high density process is tailored to minimize onstate resistance at low gate drive conditions. This device is designed especially for battery power applications such as notebook computers and cellular phones. This device has excellent on-state resistance even at gate drive voltages as low as 2.5 volts. Features -0.65 A, -25 V. RDS(ON) = 1.1 Ω @ VGS = -4.5 V RDS(ON) = 1.5 Ω @ VGS = -2.7 V. Very low gate drive requirements allowing direct operation in 3V cirucuits (VGS(th) <1.5 V). Gate-Source Zener for ESD ruggedness (>6 kV Human Body Model). Compact industry standard SC70-6 surface mount package. Applications Power Management Load switch Signal switch D D S 1 6 2 5 SC70-6 D D G 3 4 Absolute Maximum Ratings Symbol V DSS V GSS ID PD T J, T stg ESD Drain-Source Voltage Gate-Source Voltage Drain Current - Continuous - Pulsed T A = 25°C unless otherwise noted Parameter Ratings -25 (Note 1a) Units V V A W °C kV ±8 -0.65 -1.8 0.75 0.48 -55 to +150 6.0 Power Dissipation for Single Operation (Note 1a) (Note 1b) Operating and Storage Junction Temperature Range Electrostatic Discharge Rating MIL-STD-883D Human Body Model (100pf/1500 Ohm) Thermal Characteristics R θJA Thermal Resistance, Junction-to-Ambient (Note 1b) 260 ...