Digital FET. FDG6304P Datasheet

FDG6304P Datasheet PDF, Equivalent


Part Number

FDG6304P

Description

Dual P-Channel/ Digital FET

Manufacture

Fairchild Semiconductor

Total Page 8 Pages
PDF Download
Download FDG6304P Datasheet


FDG6304P Datasheet
July 1999
FDG6304P
Dual P-Channel, Digital FET
General Description
These dual P-Channel logic level enhancement mode
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. This device has been
designed especially for low voltage applications as a
replacement for bipolar digital transistors and small
signal MOSFETs.
Features
-25 V, -0.41 A continuous, -1.5 A peak.
RDS(ON) = 1.1 @ VGS= -4.5 V,
RDS(ON) = 1.5 @ VGS= -2.7 V.
Very low level gate drive requirements allowing direct
operation in 3 V circuits (VGS(th) < 1.5 V).
Gate-Source Zener for ESD ruggedness
(>6kV Human Body Model).
Compact industry standard SC70-6 surface
mount package.
SC70-6
SOT-23
SuperSOTTM-6
SuperSOTTM-8
SO-8
SOT-223
S2
G2
D1
.04
1 or 4 *
SC70-6
D2
S1 G1
2 or 5
3 or 6
*The pinouts are symmetrical; pin 1 and 4 are interchangeable.
Units inside the carrier can be of either orientation and will not affect the functionality of the device.
Absolute Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter
VDSS Drain-Source Voltage
VGSS Gate-Source Voltage
ID Drain/Output Current - Continuous
- Pulsed
PD Maximum Power Dissipation
(Note 1)
TJ,TSTG Operating and Storage Temperature Range
ESD Electrostatic Discharge Rating MIL-STD-883D
Human Body Model (100 pF / 1500 )
THERMAL CHARACTERISTICS
RθJA Thermal Resistance, Junction-to-Ambient (Note 1)
FDG6304P
-25
-8
-0.41
-1.5
0.3
-55 to 150
6.0
415
6 or 3
5 or 2
4 or 1 *
Units
V
V
A
W
°C
kV
°C/W
FDG6304P Rev.E1

FDG6304P Datasheet
Electrical Characteristics (TA = 25 OC unless otherwise noted)
Symbol
Parameter
Conditions
Min Typ Max
Units
OFF CHARACTERISTICS
BVDSS
BVDSS/TJ
IDSS
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coefficient
Zero Gate Voltage Drain Current
IGSS Gate - Body Leakage Current
ON CHARACTERISTICS (Note 2)
VGS = 0 V, ID = -250 µA
ID = -250 µA, Referenced to 25oC
-25
-22
V
mV / oC
VDS = -20 V, VGS = 0 V
-1 µA
TJ = 55°C
-10 µA
VGS = -8 V, VDS = 0 V
-100 nA
VGS(th)
VGS(th)/TJ
RDS(ON)
Gate Threshold Voltage
Gate Threshold Voltage Temp.Coefficient
Static Drain-Source On-Resistance
ID(ON) On-State Drain Current
gFS Forward Transconductance
DYNAMIC CHARACTERISTICS
VDS = VGS, ID = -250 µA
ID = -250 µA, Referenced to 25oC
VGS = -4.5 V, ID = -0.41 A
TJ =125°C
VGS = -2.7 V, ID = -0.25 A
VGS = -4.5 V, VDS = -5 V
VDS = -5 V, ID = -0.41 A
-0.65
-1.5
-0.82
2
0.85
1.2
1.15
0.9
-1.5 V
mV / oC
1.1
1.9
1.5
A
S
Ciss Input Capacitance
Coss Output Capacitance
Crss Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS (Note 2)
VDS = 10 V, VGS = 0 V,
f = 1.0 MHz
62 pF
34 pF
10 pF
tD(on) Turn - On Delay Time
tr Turn - On Rise Time
VDD = -5 V, ID = -0.5 A,
VGS = -4.5 V, RGEN = 6
tD(off) Turn - Off Delay Time
tf Turn - Off Fall Time
Qg Total Gate Charge
Qgs Gate-Source Charge
VDS = -5 V, ID = -0.41 A,
VGS = -4.5 V
Qgd Gate-Drain Charge
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS
7 15
8 16
55 80
35 60
1.1 1.5
0.31
0.29
ns
ns
ns
ns
nC
nC
nC
IS Maximum Continuous Source Current
-0.25
A
VSD Drain-Source Diode Forward Voltage
VGS = 0 V, IS = -0.25 A (Note 2)
-0.85 -1.2
V
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed
by design while RθCA is determined by the user's board design. RθJA = 415OC/W on minimum pad mounting on FR-4 board in still air.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%.
FDG6304P Rev.E1


Features Datasheet pdf July 1999 FDG6304P Dual P-Channel, Digi tal FET General Description These dual P-Channel logic level enhancement mode field effect transistors are produced u sing Fairchild's proprietary, high cell density, DMOS technology. This very hi gh density process is especially tailor ed to minimize on-state resistance. Thi s device has been designed especially f or low voltage applications as a replac ement for bipolar digital transistors a nd small signal MOSFETs. Features -25 V, -0.41 A continuous, -1.5 A peak. RDS (ON) = 1.1 Ω @ VGS= -4.5 V, RDS(ON) = 1.5 Ω @ VGS= -2.7 V. Very low level gate drive requirements allowing direct operation in 3 V circuits (VGS(th) < 1 .5 V). Gate-Source Zener for ESD rugged ness (>6kV Human Body Model). Compact i ndustry standard SC70-6 surface mount p ackage. SC70-6 SOT-23 SuperSOTTM-6 SuperSOTTM-8 SO-8 SOT-223 D1 G2 S2 .04 D2 1 or 4 * 6 or 3 2 or 5 5 o r 2 SC70-6 S1 G1 3 or 6 4 or 1 * *The pinouts are symmetrical; pin 1 and 4 are interchangeable. Un.
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